ca26d28bba
The hardware provides us with separate threads for binning and rendering, and the existing model waits for them both to complete before submitting the next job. Splitting the binning and rendering submissions reduces idle time and gives us approx 20-30% speedup with some x11perf tests such as -line10 and -tilerect1. Improves openarena performance by 1.01897% +/- 0.247857% (n=16). Thanks to anholt for suggesting this. v2: Rebase on the spurious resets fix (change by anholt). Signed-off-by: Varad Gautam <varadgautam@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net>
499 lines
14 KiB
C
499 lines
14 KiB
C
/*
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* Copyright (C) 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "drmP.h"
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#include "drm_gem_cma_helper.h"
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struct vc4_dev {
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struct drm_device *dev;
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struct vc4_hdmi *hdmi;
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struct vc4_hvs *hvs;
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struct vc4_crtc *crtc[3];
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struct vc4_v3d *v3d;
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struct drm_fbdev_cma *fbdev;
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struct vc4_hang_state *hang_state;
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/* The kernel-space BO cache. Tracks buffers that have been
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* unreferenced by all other users (refcounts of 0!) but not
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* yet freed, so we can do cheap allocations.
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*/
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struct vc4_bo_cache {
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/* Array of list heads for entries in the BO cache,
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* based on number of pages, so we can do O(1) lookups
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* in the cache when allocating.
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*/
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struct list_head *size_list;
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uint32_t size_list_size;
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/* List of all BOs in the cache, ordered by age, so we
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* can do O(1) lookups when trying to free old
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* buffers.
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*/
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struct list_head time_list;
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struct work_struct time_work;
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struct timer_list time_timer;
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} bo_cache;
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struct vc4_bo_stats {
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u32 num_allocated;
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u32 size_allocated;
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u32 num_cached;
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u32 size_cached;
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} bo_stats;
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/* Protects bo_cache and the BO stats. */
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struct mutex bo_lock;
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/* Sequence number for the last job queued in bin_job_list.
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* Starts at 0 (no jobs emitted).
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*/
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uint64_t emit_seqno;
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/* Sequence number for the last completed job on the GPU.
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* Starts at 0 (no jobs completed).
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*/
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uint64_t finished_seqno;
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/* List of all struct vc4_exec_info for jobs to be executed in
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* the binner. The first job in the list is the one currently
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* programmed into ct0ca for execution.
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*/
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struct list_head bin_job_list;
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/* List of all struct vc4_exec_info for jobs that have
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* completed binning and are ready for rendering. The first
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* job in the list is the one currently programmed into ct1ca
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* for execution.
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*/
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struct list_head render_job_list;
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/* List of the finished vc4_exec_infos waiting to be freed by
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* job_done_work.
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*/
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struct list_head job_done_list;
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/* Spinlock used to synchronize the job_list and seqno
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* accesses between the IRQ handler and GEM ioctls.
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*/
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spinlock_t job_lock;
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wait_queue_head_t job_wait_queue;
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struct work_struct job_done_work;
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/* List of struct vc4_seqno_cb for callbacks to be made from a
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* workqueue when the given seqno is passed.
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*/
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struct list_head seqno_cb_list;
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/* The binner overflow memory that's currently set up in
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* BPOA/BPOS registers. When overflow occurs and a new one is
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* allocated, the previous one will be moved to
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* vc4->current_exec's free list.
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*/
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struct vc4_bo *overflow_mem;
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struct work_struct overflow_mem_work;
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int power_refcount;
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/* Mutex controlling the power refcount. */
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struct mutex power_lock;
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struct {
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struct timer_list timer;
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struct work_struct reset_work;
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} hangcheck;
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struct semaphore async_modeset;
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};
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static inline struct vc4_dev *
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to_vc4_dev(struct drm_device *dev)
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{
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return (struct vc4_dev *)dev->dev_private;
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}
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struct vc4_bo {
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struct drm_gem_cma_object base;
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/* seqno of the last job to render to this BO. */
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uint64_t seqno;
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/* List entry for the BO's position in either
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* vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
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*/
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struct list_head unref_head;
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/* Time in jiffies when the BO was put in vc4->bo_cache. */
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unsigned long free_time;
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/* List entry for the BO's position in vc4_dev->bo_cache.size_list */
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struct list_head size_head;
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/* Struct for shader validation state, if created by
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* DRM_IOCTL_VC4_CREATE_SHADER_BO.
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*/
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struct vc4_validated_shader_info *validated_shader;
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};
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static inline struct vc4_bo *
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to_vc4_bo(struct drm_gem_object *bo)
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{
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return (struct vc4_bo *)bo;
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}
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struct vc4_seqno_cb {
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struct work_struct work;
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uint64_t seqno;
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void (*func)(struct vc4_seqno_cb *cb);
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};
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struct vc4_v3d {
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struct vc4_dev *vc4;
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struct platform_device *pdev;
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void __iomem *regs;
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};
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struct vc4_hvs {
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struct platform_device *pdev;
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void __iomem *regs;
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u32 __iomem *dlist;
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/* Memory manager for CRTCs to allocate space in the display
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* list. Units are dwords.
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*/
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struct drm_mm dlist_mm;
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/* Memory manager for the LBM memory used by HVS scaling. */
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struct drm_mm lbm_mm;
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spinlock_t mm_lock;
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struct drm_mm_node mitchell_netravali_filter;
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};
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struct vc4_plane {
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struct drm_plane base;
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};
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static inline struct vc4_plane *
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to_vc4_plane(struct drm_plane *plane)
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{
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return (struct vc4_plane *)plane;
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}
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enum vc4_encoder_type {
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VC4_ENCODER_TYPE_HDMI,
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VC4_ENCODER_TYPE_VEC,
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VC4_ENCODER_TYPE_DSI0,
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VC4_ENCODER_TYPE_DSI1,
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VC4_ENCODER_TYPE_SMI,
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VC4_ENCODER_TYPE_DPI,
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};
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struct vc4_encoder {
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struct drm_encoder base;
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enum vc4_encoder_type type;
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u32 clock_select;
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};
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static inline struct vc4_encoder *
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to_vc4_encoder(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct vc4_encoder, base);
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}
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#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
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#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
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#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
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#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
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struct vc4_exec_info {
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/* Sequence number for this bin/render job. */
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uint64_t seqno;
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/* Last current addresses the hardware was processing when the
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* hangcheck timer checked on us.
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*/
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uint32_t last_ct0ca, last_ct1ca;
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/* Kernel-space copy of the ioctl arguments */
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struct drm_vc4_submit_cl *args;
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/* This is the array of BOs that were looked up at the start of exec.
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* Command validation will use indices into this array.
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*/
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struct drm_gem_cma_object **bo;
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uint32_t bo_count;
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/* Pointers for our position in vc4->job_list */
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struct list_head head;
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/* List of other BOs used in the job that need to be released
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* once the job is complete.
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*/
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struct list_head unref_list;
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/* Current unvalidated indices into @bo loaded by the non-hardware
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* VC4_PACKET_GEM_HANDLES.
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*/
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uint32_t bo_index[2];
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/* This is the BO where we store the validated command lists, shader
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* records, and uniforms.
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*/
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struct drm_gem_cma_object *exec_bo;
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/**
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* This tracks the per-shader-record state (packet 64) that
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* determines the length of the shader record and the offset
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* it's expected to be found at. It gets read in from the
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* command lists.
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*/
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struct vc4_shader_state {
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uint32_t addr;
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/* Maximum vertex index referenced by any primitive using this
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* shader state.
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*/
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uint32_t max_index;
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} *shader_state;
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/** How many shader states the user declared they were using. */
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uint32_t shader_state_size;
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/** How many shader state records the validator has seen. */
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uint32_t shader_state_count;
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bool found_tile_binning_mode_config_packet;
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bool found_start_tile_binning_packet;
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bool found_increment_semaphore_packet;
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bool found_flush;
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uint8_t bin_tiles_x, bin_tiles_y;
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struct drm_gem_cma_object *tile_bo;
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uint32_t tile_alloc_offset;
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/**
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* Computed addresses pointing into exec_bo where we start the
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* bin thread (ct0) and render thread (ct1).
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*/
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uint32_t ct0ca, ct0ea;
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uint32_t ct1ca, ct1ea;
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/* Pointer to the unvalidated bin CL (if present). */
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void *bin_u;
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/* Pointers to the shader recs. These paddr gets incremented as CL
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* packets are relocated in validate_gl_shader_state, and the vaddrs
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* (u and v) get incremented and size decremented as the shader recs
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* themselves are validated.
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*/
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void *shader_rec_u;
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void *shader_rec_v;
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uint32_t shader_rec_p;
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uint32_t shader_rec_size;
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/* Pointers to the uniform data. These pointers are incremented, and
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* size decremented, as each batch of uniforms is uploaded.
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*/
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void *uniforms_u;
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void *uniforms_v;
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uint32_t uniforms_p;
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uint32_t uniforms_size;
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};
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static inline struct vc4_exec_info *
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vc4_first_bin_job(struct vc4_dev *vc4)
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{
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if (list_empty(&vc4->bin_job_list))
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return NULL;
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return list_first_entry(&vc4->bin_job_list, struct vc4_exec_info, head);
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}
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static inline struct vc4_exec_info *
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vc4_first_render_job(struct vc4_dev *vc4)
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{
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if (list_empty(&vc4->render_job_list))
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return NULL;
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return list_first_entry(&vc4->render_job_list,
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struct vc4_exec_info, head);
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}
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/**
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* struct vc4_texture_sample_info - saves the offsets into the UBO for texture
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* setup parameters.
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*
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* This will be used at draw time to relocate the reference to the texture
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* contents in p0, and validate that the offset combined with
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* width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
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* Note that the hardware treats unprovided config parameters as 0, so not all
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* of them need to be set up for every texure sample, and we'll store ~0 as
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* the offset to mark the unused ones.
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*
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* See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
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* Setup") for definitions of the texture parameters.
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*/
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struct vc4_texture_sample_info {
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bool is_direct;
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uint32_t p_offset[4];
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};
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/**
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* struct vc4_validated_shader_info - information about validated shaders that
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* needs to be used from command list validation.
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*
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* For a given shader, each time a shader state record references it, we need
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* to verify that the shader doesn't read more uniforms than the shader state
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* record's uniform BO pointer can provide, and we need to apply relocations
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* and validate the shader state record's uniforms that define the texture
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* samples.
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*/
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struct vc4_validated_shader_info {
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uint32_t uniforms_size;
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uint32_t uniforms_src_size;
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uint32_t num_texture_samples;
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struct vc4_texture_sample_info *texture_samples;
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};
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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if (!(COND)) \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && drm_can_sleep()) { \
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msleep(W); \
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} else { \
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cpu_relax(); \
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} \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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/* vc4_bo.c */
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struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
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void vc4_free_object(struct drm_gem_object *gem_obj);
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struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
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bool from_cache);
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int vc4_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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struct dma_buf *vc4_prime_export(struct drm_device *dev,
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struct drm_gem_object *obj, int flags);
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int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
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int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
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void *vc4_prime_vmap(struct drm_gem_object *obj);
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void vc4_bo_cache_init(struct drm_device *dev);
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void vc4_bo_cache_destroy(struct drm_device *dev);
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int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
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/* vc4_crtc.c */
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extern struct platform_driver vc4_crtc_driver;
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int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id);
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void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
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/* vc4_debugfs.c */
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int vc4_debugfs_init(struct drm_minor *minor);
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void vc4_debugfs_cleanup(struct drm_minor *minor);
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/* vc4_drv.c */
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void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
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/* vc4_gem.c */
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void vc4_gem_init(struct drm_device *dev);
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void vc4_gem_destroy(struct drm_device *dev);
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int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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void vc4_submit_next_bin_job(struct drm_device *dev);
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void vc4_submit_next_render_job(struct drm_device *dev);
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void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
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int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
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uint64_t timeout_ns, bool interruptible);
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void vc4_job_handle_completed(struct vc4_dev *vc4);
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int vc4_queue_seqno_cb(struct drm_device *dev,
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struct vc4_seqno_cb *cb, uint64_t seqno,
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void (*func)(struct vc4_seqno_cb *cb));
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/* vc4_hdmi.c */
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extern struct platform_driver vc4_hdmi_driver;
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int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_irq.c */
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irqreturn_t vc4_irq(int irq, void *arg);
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void vc4_irq_preinstall(struct drm_device *dev);
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int vc4_irq_postinstall(struct drm_device *dev);
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void vc4_irq_uninstall(struct drm_device *dev);
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void vc4_irq_reset(struct drm_device *dev);
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/* vc4_hvs.c */
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extern struct platform_driver vc4_hvs_driver;
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void vc4_hvs_dump_state(struct drm_device *dev);
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int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_kms.c */
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int vc4_kms_load(struct drm_device *dev);
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/* vc4_plane.c */
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struct drm_plane *vc4_plane_init(struct drm_device *dev,
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enum drm_plane_type type);
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u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
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u32 vc4_plane_dlist_size(struct drm_plane_state *state);
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void vc4_plane_async_set_fb(struct drm_plane *plane,
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struct drm_framebuffer *fb);
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/* vc4_v3d.c */
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extern struct platform_driver vc4_v3d_driver;
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int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
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int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
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/* vc4_validate.c */
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int
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vc4_validate_bin_cl(struct drm_device *dev,
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void *validated,
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void *unvalidated,
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struct vc4_exec_info *exec);
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int
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vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
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struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
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uint32_t hindex);
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int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
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bool vc4_check_tex_size(struct vc4_exec_info *exec,
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struct drm_gem_cma_object *fbo,
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uint32_t offset, uint8_t tiling_format,
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uint32_t width, uint32_t height, uint8_t cpp);
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/* vc4_validate_shader.c */
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struct vc4_validated_shader_info *
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vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
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