267 lines
9.9 KiB
C
267 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hantro VPU codec driver
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*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <asm/unaligned.h>
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#include <linux/bitfield.h>
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#include <media/v4l2-mem2mem.h>
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#include "hantro.h"
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#include "hantro_hw.h"
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#define VDPU_SWREG(nr) ((nr) * 4)
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#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63)
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#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64)
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#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61)
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#define VDPU_REG_REFER0_BASE VDPU_SWREG(131)
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#define VDPU_REG_REFER2_BASE VDPU_SWREG(134)
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#define VDPU_REG_REFER3_BASE VDPU_SWREG(135)
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#define VDPU_REG_REFER1_BASE VDPU_SWREG(148)
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#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0)
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#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0)
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#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0)
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#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0)
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#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1))
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#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
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#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
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#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17))
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#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8))
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#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0))
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#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0))
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#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0)
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#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0)
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#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0)
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#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0)
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#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0)
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#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0)
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#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0)
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#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16))
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#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8))
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#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0))
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#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0)
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#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0)
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#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0)
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#define VDPU_REG_PIC_B_E(v) ((v) ? BIT(15) : 0)
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#define VDPU_REG_PIC_INTER_E(v) ((v) ? BIT(14) : 0)
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#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0)
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#define VDPU_REG_FWD_INTERLACE_E(v) ((v) ? BIT(12) : 0)
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#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0)
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#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0)
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#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0)
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#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
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#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
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#define VDPU_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
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#define VDPU_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
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#define VDPU_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
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#define VDPU_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
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#define VDPU_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
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#define VDPU_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
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#define VDPU_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
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#define VDPU_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
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#define VDPU_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
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#define VDPU_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
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#define VDPU_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
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#define VDPU_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
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#define VDPU_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
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#define VDPU_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
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#define VDPU_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
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#define PICT_TOP_FIELD 1
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#define PICT_BOTTOM_FIELD 2
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#define PICT_FRAME 3
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static void
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rk3399_vpu_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
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struct hantro_ctx *ctx)
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{
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struct v4l2_ctrl_mpeg2_quantization *quantization;
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quantization = hantro_get_ctrl(ctx,
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V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
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hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, quantization);
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vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
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VDPU_REG_QTABLE_BASE);
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}
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static void
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rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
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struct hantro_ctx *ctx,
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struct vb2_buffer *src_buf,
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struct vb2_buffer *dst_buf,
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const struct v4l2_mpeg2_sequence *sequence,
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const struct v4l2_mpeg2_picture *picture,
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const struct v4l2_ctrl_mpeg2_slice_params *slice_params)
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{
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dma_addr_t forward_addr = 0, backward_addr = 0;
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dma_addr_t current_addr, addr;
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struct vb2_queue *vq;
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vq = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
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switch (picture->picture_coding_type) {
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case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
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backward_addr = hantro_get_ref(vq,
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slice_params->backward_ref_ts);
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/* fall-through */
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case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
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forward_addr = hantro_get_ref(vq,
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slice_params->forward_ref_ts);
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}
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/* Source bitstream buffer */
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addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
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vdpu_write_relaxed(vpu, addr, VDPU_REG_RLC_VLC_BASE);
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/* Destination frame buffer */
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addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
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current_addr = addr;
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if (picture->picture_structure == PICT_BOTTOM_FIELD)
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addr += ALIGN(ctx->dst_fmt.width, 16);
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vdpu_write_relaxed(vpu, addr, VDPU_REG_DEC_OUT_BASE);
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if (!forward_addr)
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forward_addr = current_addr;
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if (!backward_addr)
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backward_addr = current_addr;
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/* Set forward ref frame (top/bottom field) */
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if (picture->picture_structure == PICT_FRAME ||
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picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B ||
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(picture->picture_structure == PICT_TOP_FIELD &&
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picture->top_field_first) ||
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(picture->picture_structure == PICT_BOTTOM_FIELD &&
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!picture->top_field_first)) {
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vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
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vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
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} else if (picture->picture_structure == PICT_TOP_FIELD) {
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vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER0_BASE);
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vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER1_BASE);
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} else if (picture->picture_structure == PICT_BOTTOM_FIELD) {
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vdpu_write_relaxed(vpu, current_addr, VDPU_REG_REFER0_BASE);
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vdpu_write_relaxed(vpu, forward_addr, VDPU_REG_REFER1_BASE);
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}
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/* Set backward ref frame (top/bottom field) */
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vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER2_BASE);
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vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
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}
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void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct vb2_v4l2_buffer *src_buf, *dst_buf;
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const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
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const struct v4l2_mpeg2_sequence *sequence;
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const struct v4l2_mpeg2_picture *picture;
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u32 reg;
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src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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/* Apply request controls if any */
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v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
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&ctx->ctrl_handler);
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slice_params = hantro_get_ctrl(ctx,
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V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
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sequence = &slice_params->sequence;
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picture = &slice_params->picture;
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reg = VDPU_REG_DEC_ADV_PRE_DIS(0) |
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VDPU_REG_DEC_SCMD_DIS(0) |
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VDPU_REG_FILTERING_DIS(1) |
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VDPU_REG_DEC_LATENCY(0);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50));
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reg = VDPU_REG_INIT_QP(1) |
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VDPU_REG_STREAM_LEN(slice_params->bit_size >> 3);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51));
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reg = VDPU_REG_APF_THRESHOLD(8) |
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VDPU_REG_STARTMB_X(0) |
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VDPU_REG_STARTMB_Y(0);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52));
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reg = VDPU_REG_DEC_MODE(5);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53));
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reg = VDPU_REG_DEC_STRENDIAN_E(1) |
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VDPU_REG_DEC_STRSWAP32_E(1) |
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VDPU_REG_DEC_OUTSWAP32_E(1) |
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VDPU_REG_DEC_INSWAP32_E(1) |
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VDPU_REG_DEC_OUT_ENDIAN(1) |
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VDPU_REG_DEC_IN_ENDIAN(1);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54));
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reg = VDPU_REG_DEC_DATA_DISC_E(0) |
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VDPU_REG_DEC_MAX_BURST(16) |
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VDPU_REG_DEC_AXI_WR_ID(0) |
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VDPU_REG_DEC_AXI_RD_ID(0);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56));
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reg = VDPU_REG_RLC_MODE_E(0) |
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VDPU_REG_PIC_INTERLACE_E(!sequence->progressive_sequence) |
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VDPU_REG_PIC_FIELDMODE_E(picture->picture_structure != PICT_FRAME) |
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VDPU_REG_PIC_B_E(picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B) |
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VDPU_REG_PIC_INTER_E(picture->picture_coding_type != V4L2_MPEG2_PICTURE_CODING_TYPE_I) |
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VDPU_REG_PIC_TOPFIELD_E(picture->picture_structure == PICT_TOP_FIELD) |
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VDPU_REG_FWD_INTERLACE_E(0) |
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VDPU_REG_WRITE_MVS_E(0) |
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VDPU_REG_DEC_TIMEOUT_E(1) |
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VDPU_REG_DEC_CLK_GATE_E(1);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57));
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reg = VDPU_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) |
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VDPU_REG_PIC_MB_HEIGHT_P(MPEG2_MB_HEIGHT(ctx->dst_fmt.height)) |
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VDPU_REG_ALT_SCAN_E(picture->alternate_scan) |
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VDPU_REG_TOPFIELDFIRST_E(picture->top_field_first);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(120));
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reg = VDPU_REG_STRM_START_BIT(slice_params->data_bit_offset) |
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VDPU_REG_QSCALE_TYPE(picture->q_scale_type) |
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VDPU_REG_CON_MV_E(picture->concealment_motion_vectors) |
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VDPU_REG_INTRA_DC_PREC(picture->intra_dc_precision) |
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VDPU_REG_INTRA_VLC_TAB(picture->intra_vlc_format) |
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VDPU_REG_FRAME_PRED_DCT(picture->frame_pred_frame_dct);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(122));
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reg = VDPU_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) |
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VDPU_REG_FCODE_FWD_HOR(picture->f_code[0][0]) |
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VDPU_REG_FCODE_FWD_VER(picture->f_code[0][1]) |
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VDPU_REG_FCODE_BWD_HOR(picture->f_code[1][0]) |
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VDPU_REG_FCODE_BWD_VER(picture->f_code[1][1]) |
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VDPU_REG_MV_ACCURACY_FWD(1) |
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VDPU_REG_MV_ACCURACY_BWD(1);
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vdpu_write_relaxed(vpu, reg, VDPU_SWREG(136));
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rk3399_vpu_mpeg2_dec_set_quantization(vpu, ctx);
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rk3399_vpu_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
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&dst_buf->vb2_buf,
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sequence, picture, slice_params);
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/* Controls no longer in-use, we can complete them */
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v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
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&ctx->ctrl_handler);
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/* Kick the watchdog and start decoding */
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schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
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reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1);
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vdpu_write(vpu, reg, VDPU_SWREG(57));
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}
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