alistair23-linux/drivers/staging/iio/Documentation/sysfs-bus-iio-impedance-analyzer-ad5933
Michael Hennerich f94aa354d6 iio: impedance-analyzer: New driver for AD5933/4 Impedance Converter, Network Analyzer
The AD5933 is a high precision impedance converter system solution
that combines an on-board frequency generator with a 12-bit, 1 MSPS,
analog-to-digital converter (ADC). The frequency generator allows an
external complex impedance to be excited with a known frequency.

The response signal from the impedance is sampled by the on-board ADC
and a discrete Fourier transform (DFT) is processed by an on-chip DSP engine.
The DFT algorithm returns a real (R) and imaginary (I) data-word at each
output frequency.

Changes since V1:

Apply list review feedback:
Consistently use poll_time_jiffies.
Use be|le cpu endian helpers where applicable.
Add various comments.

Changes since V2:

Fix KernelVersion tag in Documentation.
Declare ad5933_default_pdata static.
Fix typos.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Acked-by: Jonathan Cameron <jic23@cam.ac.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-23 13:37:02 -07:00

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What: /sys/bus/iio/devices/iio:deviceX/outY_freq_start
KernelVersion: 3.1.0
Contact: linux-iio@vger.kernel.org
Description:
Frequency sweep start frequency in Hz.
What: /sys/bus/iio/devices/iio:deviceX/outY_freq_increment
KernelVersion: 3.1.0
Contact: linux-iio@vger.kernel.org
Description:
Frequency increment in Hz (step size) between consecutive
frequency points along the sweep.
What: /sys/bus/iio/devices/iio:deviceX/outY_freq_points
KernelVersion: 3.1.0
Contact: linux-iio@vger.kernel.org
Description:
Number of frequency points (steps) in the frequency sweep.
This value, in conjunction with the outY_freq_start and the
outY_freq_increment, determines the frequency sweep range
for the sweep operation.
What: /sys/bus/iio/devices/iio:deviceX/outY_settling_cycles
KernelVersion: 3.1.0
Contact: linux-iio@vger.kernel.org
Description:
Number of output excitation cycles (settling time cycles)
that are allowed to pass through the unknown impedance,
after each frequency increment, and before the ADC is triggered
to perform a conversion sequence of the response signal.