![YoungJun Cho](/assets/img/avatar_default.png)
This patch removes vaddr member from exynos_drm_overlay structure and also relevant codes for code cleanup. Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
1084 lines
26 KiB
C
1084 lines
26 KiB
C
/* exynos_drm_fimd.c
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*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Authors:
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Inki Dae <inki.dae@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <drm/drmP.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <video/samsung_fimd.h>
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#include <drm/exynos_drm.h>
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#include "exynos_drm_drv.h"
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#include "exynos_drm_fbdev.h"
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_iommu.h"
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/*
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* FIMD is stand for Fully Interactive Mobile Display and
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* as a display controller, it transfers contents drawn on memory
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* to a LCD Panel through Display Interfaces such as RGB or
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* CPU Interface.
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*/
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/* position control register for hardware window 0, 2 ~ 4.*/
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#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
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#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
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/* size control register for hardware window 0. */
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#define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
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/* alpha control register for hardware window 1 ~ 4. */
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#define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
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/* size control register for hardware window 1 ~ 4. */
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#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
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#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
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#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
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#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
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/* color key control register for hardware window 1 ~ 4. */
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#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
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/* color key value register for hardware window 1 ~ 4. */
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#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
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/* FIMD has totally five hardware windows. */
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#define WINDOWS_NR 5
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#define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
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struct fimd_driver_data {
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unsigned int timing_base;
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};
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static struct fimd_driver_data exynos4_fimd_driver_data = {
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.timing_base = 0x0,
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};
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static struct fimd_driver_data exynos5_fimd_driver_data = {
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.timing_base = 0x20000,
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};
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struct fimd_win_data {
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unsigned int offset_x;
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unsigned int offset_y;
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unsigned int ovl_width;
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unsigned int ovl_height;
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unsigned int fb_width;
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unsigned int fb_height;
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unsigned int bpp;
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dma_addr_t dma_addr;
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unsigned int buf_offsize;
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unsigned int line_size; /* bytes */
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bool enabled;
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bool resume;
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};
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struct fimd_context {
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struct exynos_drm_subdrv subdrv;
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int irq;
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struct drm_crtc *crtc;
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struct clk *bus_clk;
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struct clk *lcd_clk;
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void __iomem *regs;
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struct fimd_win_data win_data[WINDOWS_NR];
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unsigned int clkdiv;
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unsigned int default_win;
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unsigned long irq_flags;
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u32 vidcon0;
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u32 vidcon1;
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bool suspended;
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struct mutex lock;
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wait_queue_head_t wait_vsync_queue;
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atomic_t wait_vsync_event;
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struct exynos_drm_panel_info *panel;
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};
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static inline struct fimd_driver_data *drm_fimd_get_driver_data(
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struct platform_device *pdev)
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{
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return (struct fimd_driver_data *)
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platform_get_device_id(pdev)->driver_data;
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}
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static bool fimd_display_is_connected(struct device *dev)
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{
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* TODO. */
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return true;
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}
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static void *fimd_get_panel(struct device *dev)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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DRM_DEBUG_KMS("%s\n", __FILE__);
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return ctx->panel;
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}
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static int fimd_check_timing(struct device *dev, void *timing)
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{
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* TODO. */
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return 0;
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}
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static int fimd_display_power_on(struct device *dev, int mode)
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{
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* TODO */
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return 0;
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}
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static struct exynos_drm_display_ops fimd_display_ops = {
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.type = EXYNOS_DISPLAY_TYPE_LCD,
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.is_connected = fimd_display_is_connected,
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.get_panel = fimd_get_panel,
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.check_timing = fimd_check_timing,
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.power_on = fimd_display_power_on,
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};
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static void fimd_dpms(struct device *subdrv_dev, int mode)
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{
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struct fimd_context *ctx = get_fimd_context(subdrv_dev);
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DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
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mutex_lock(&ctx->lock);
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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/*
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* enable fimd hardware only if suspended status.
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*
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* P.S. fimd_dpms function would be called at booting time so
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* clk_enable could be called double time.
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*/
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if (ctx->suspended)
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pm_runtime_get_sync(subdrv_dev);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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if (!ctx->suspended)
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pm_runtime_put_sync(subdrv_dev);
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break;
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default:
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DRM_DEBUG_KMS("unspecified mode %d\n", mode);
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break;
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}
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mutex_unlock(&ctx->lock);
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}
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static void fimd_apply(struct device *subdrv_dev)
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{
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struct fimd_context *ctx = get_fimd_context(subdrv_dev);
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struct exynos_drm_manager *mgr = ctx->subdrv.manager;
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struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
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struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
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struct fimd_win_data *win_data;
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int i;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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for (i = 0; i < WINDOWS_NR; i++) {
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win_data = &ctx->win_data[i];
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if (win_data->enabled && (ovl_ops && ovl_ops->commit))
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ovl_ops->commit(subdrv_dev, i);
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}
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if (mgr_ops && mgr_ops->commit)
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mgr_ops->commit(subdrv_dev);
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}
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static void fimd_commit(struct device *dev)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct exynos_drm_panel_info *panel = ctx->panel;
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struct fb_videomode *timing = &panel->timing;
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struct fimd_driver_data *driver_data;
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struct platform_device *pdev = to_platform_device(dev);
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u32 val;
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driver_data = drm_fimd_get_driver_data(pdev);
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if (ctx->suspended)
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return;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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/* setup polarity values from machine code. */
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writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
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/* setup vertical timing values. */
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val = VIDTCON0_VBPD(timing->upper_margin - 1) |
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VIDTCON0_VFPD(timing->lower_margin - 1) |
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VIDTCON0_VSPW(timing->vsync_len - 1);
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writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
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/* setup horizontal timing values. */
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val = VIDTCON1_HBPD(timing->left_margin - 1) |
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VIDTCON1_HFPD(timing->right_margin - 1) |
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VIDTCON1_HSPW(timing->hsync_len - 1);
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writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
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/* setup horizontal and vertical display size. */
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val = VIDTCON2_LINEVAL(timing->yres - 1) |
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VIDTCON2_HOZVAL(timing->xres - 1);
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writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
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/* setup clock source, clock divider, enable dma. */
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val = ctx->vidcon0;
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val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
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if (ctx->clkdiv > 1)
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val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
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else
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val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
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/*
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* fields of register with prefix '_F' would be updated
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* at vsync(same as dma start)
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*/
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val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
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writel(val, ctx->regs + VIDCON0);
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}
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static int fimd_enable_vblank(struct device *dev)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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u32 val;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (ctx->suspended)
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return -EPERM;
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if (!test_and_set_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val |= VIDINTCON0_INT_ENABLE;
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val |= VIDINTCON0_INT_FRAME;
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val &= ~VIDINTCON0_FRAMESEL0_MASK;
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val |= VIDINTCON0_FRAMESEL0_VSYNC;
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val &= ~VIDINTCON0_FRAMESEL1_MASK;
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val |= VIDINTCON0_FRAMESEL1_NONE;
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writel(val, ctx->regs + VIDINTCON0);
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}
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return 0;
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}
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static void fimd_disable_vblank(struct device *dev)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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u32 val;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (ctx->suspended)
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return;
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if (test_and_clear_bit(0, &ctx->irq_flags)) {
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val = readl(ctx->regs + VIDINTCON0);
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val &= ~VIDINTCON0_INT_FRAME;
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val &= ~VIDINTCON0_INT_ENABLE;
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writel(val, ctx->regs + VIDINTCON0);
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}
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}
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static void fimd_wait_for_vblank(struct device *dev)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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if (ctx->suspended)
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return;
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atomic_set(&ctx->wait_vsync_event, 1);
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/*
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* wait for FIMD to signal VSYNC interrupt or return after
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* timeout which is set to 50ms (refresh rate of 20).
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*/
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if (!wait_event_timeout(ctx->wait_vsync_queue,
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!atomic_read(&ctx->wait_vsync_event),
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DRM_HZ/20))
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DRM_DEBUG_KMS("vblank wait timed out.\n");
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}
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static struct exynos_drm_manager_ops fimd_manager_ops = {
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.dpms = fimd_dpms,
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.apply = fimd_apply,
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.commit = fimd_commit,
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.enable_vblank = fimd_enable_vblank,
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.disable_vblank = fimd_disable_vblank,
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.wait_for_vblank = fimd_wait_for_vblank,
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};
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static void fimd_win_mode_set(struct device *dev,
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struct exynos_drm_overlay *overlay)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data;
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int win;
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unsigned long offset;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (!overlay) {
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dev_err(dev, "overlay is NULL\n");
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return;
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}
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win = overlay->zpos;
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if (win == DEFAULT_ZPOS)
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win = ctx->default_win;
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if (win < 0 || win > WINDOWS_NR)
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return;
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offset = overlay->fb_x * (overlay->bpp >> 3);
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offset += overlay->fb_y * overlay->pitch;
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DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
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win_data = &ctx->win_data[win];
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win_data->offset_x = overlay->crtc_x;
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win_data->offset_y = overlay->crtc_y;
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win_data->ovl_width = overlay->crtc_width;
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win_data->ovl_height = overlay->crtc_height;
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win_data->fb_width = overlay->fb_width;
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win_data->fb_height = overlay->fb_height;
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win_data->dma_addr = overlay->dma_addr[0] + offset;
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win_data->bpp = overlay->bpp;
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win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
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(overlay->bpp >> 3);
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win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
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DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
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win_data->offset_x, win_data->offset_y);
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DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
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win_data->ovl_width, win_data->ovl_height);
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DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
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DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
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overlay->fb_width, overlay->crtc_width);
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}
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static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data = &ctx->win_data[win];
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unsigned long val;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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val = WINCONx_ENWIN;
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switch (win_data->bpp) {
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case 1:
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val |= WINCON0_BPPMODE_1BPP;
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val |= WINCONx_BITSWP;
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val |= WINCONx_BURSTLEN_4WORD;
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break;
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case 2:
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val |= WINCON0_BPPMODE_2BPP;
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val |= WINCONx_BITSWP;
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val |= WINCONx_BURSTLEN_8WORD;
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break;
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case 4:
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val |= WINCON0_BPPMODE_4BPP;
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val |= WINCONx_BITSWP;
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val |= WINCONx_BURSTLEN_8WORD;
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break;
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case 8:
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val |= WINCON0_BPPMODE_8BPP_PALETTE;
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val |= WINCONx_BURSTLEN_8WORD;
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val |= WINCONx_BYTSWP;
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break;
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case 16:
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val |= WINCON0_BPPMODE_16BPP_565;
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val |= WINCONx_HAWSWP;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case 24:
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val |= WINCON0_BPPMODE_24BPP_888;
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val |= WINCONx_WSWP;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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case 32:
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val |= WINCON1_BPPMODE_28BPP_A4888
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| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
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val |= WINCONx_WSWP;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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default:
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DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
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val |= WINCON0_BPPMODE_24BPP_888;
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val |= WINCONx_WSWP;
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val |= WINCONx_BURSTLEN_16WORD;
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break;
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}
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DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
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writel(val, ctx->regs + WINCON(win));
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}
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static void fimd_win_set_colkey(struct device *dev, unsigned int win)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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unsigned int keycon0 = 0, keycon1 = 0;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
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WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
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keycon1 = WxKEYCON1_COLVAL(0xffffffff);
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writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
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writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
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}
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static void fimd_win_commit(struct device *dev, int zpos)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data;
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int win = zpos;
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unsigned long val, alpha, size;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (ctx->suspended)
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return;
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if (win == DEFAULT_ZPOS)
|
|
win = ctx->default_win;
|
|
|
|
if (win < 0 || win > WINDOWS_NR)
|
|
return;
|
|
|
|
win_data = &ctx->win_data[win];
|
|
|
|
/*
|
|
* SHADOWCON register is used for enabling timing.
|
|
*
|
|
* for example, once only width value of a register is set,
|
|
* if the dma is started then fimd hardware could malfunction so
|
|
* with protect window setting, the register fields with prefix '_F'
|
|
* wouldn't be updated at vsync also but updated once unprotect window
|
|
* is set.
|
|
*/
|
|
|
|
/* protect windows */
|
|
val = readl(ctx->regs + SHADOWCON);
|
|
val |= SHADOWCON_WINx_PROTECT(win);
|
|
writel(val, ctx->regs + SHADOWCON);
|
|
|
|
/* buffer start address */
|
|
val = (unsigned long)win_data->dma_addr;
|
|
writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
|
|
|
|
/* buffer end address */
|
|
size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
|
|
val = (unsigned long)(win_data->dma_addr + size);
|
|
writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
|
|
|
|
DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
|
|
(unsigned long)win_data->dma_addr, val, size);
|
|
DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
|
|
win_data->ovl_width, win_data->ovl_height);
|
|
|
|
/* buffer size */
|
|
val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
|
|
VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
|
|
writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
|
|
|
|
/* OSD position */
|
|
val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
|
|
VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
|
|
writel(val, ctx->regs + VIDOSD_A(win));
|
|
|
|
val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
|
|
win_data->ovl_width - 1) |
|
|
VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
|
|
win_data->ovl_height - 1);
|
|
writel(val, ctx->regs + VIDOSD_B(win));
|
|
|
|
DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
|
|
win_data->offset_x, win_data->offset_y,
|
|
win_data->offset_x + win_data->ovl_width - 1,
|
|
win_data->offset_y + win_data->ovl_height - 1);
|
|
|
|
/* hardware window 0 doesn't support alpha channel. */
|
|
if (win != 0) {
|
|
/* OSD alpha */
|
|
alpha = VIDISD14C_ALPHA1_R(0xf) |
|
|
VIDISD14C_ALPHA1_G(0xf) |
|
|
VIDISD14C_ALPHA1_B(0xf);
|
|
|
|
writel(alpha, ctx->regs + VIDOSD_C(win));
|
|
}
|
|
|
|
/* OSD size */
|
|
if (win != 3 && win != 4) {
|
|
u32 offset = VIDOSD_D(win);
|
|
if (win == 0)
|
|
offset = VIDOSD_C_SIZE_W0;
|
|
val = win_data->ovl_width * win_data->ovl_height;
|
|
writel(val, ctx->regs + offset);
|
|
|
|
DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
|
|
}
|
|
|
|
fimd_win_set_pixfmt(dev, win);
|
|
|
|
/* hardware window 0 doesn't support color key. */
|
|
if (win != 0)
|
|
fimd_win_set_colkey(dev, win);
|
|
|
|
/* wincon */
|
|
val = readl(ctx->regs + WINCON(win));
|
|
val |= WINCONx_ENWIN;
|
|
writel(val, ctx->regs + WINCON(win));
|
|
|
|
/* Enable DMA channel and unprotect windows */
|
|
val = readl(ctx->regs + SHADOWCON);
|
|
val |= SHADOWCON_CHx_ENABLE(win);
|
|
val &= ~SHADOWCON_WINx_PROTECT(win);
|
|
writel(val, ctx->regs + SHADOWCON);
|
|
|
|
win_data->enabled = true;
|
|
}
|
|
|
|
static void fimd_win_disable(struct device *dev, int zpos)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
struct fimd_win_data *win_data;
|
|
int win = zpos;
|
|
u32 val;
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
if (win == DEFAULT_ZPOS)
|
|
win = ctx->default_win;
|
|
|
|
if (win < 0 || win > WINDOWS_NR)
|
|
return;
|
|
|
|
win_data = &ctx->win_data[win];
|
|
|
|
if (ctx->suspended) {
|
|
/* do not resume this window*/
|
|
win_data->resume = false;
|
|
return;
|
|
}
|
|
|
|
/* protect windows */
|
|
val = readl(ctx->regs + SHADOWCON);
|
|
val |= SHADOWCON_WINx_PROTECT(win);
|
|
writel(val, ctx->regs + SHADOWCON);
|
|
|
|
/* wincon */
|
|
val = readl(ctx->regs + WINCON(win));
|
|
val &= ~WINCONx_ENWIN;
|
|
writel(val, ctx->regs + WINCON(win));
|
|
|
|
/* unprotect windows */
|
|
val = readl(ctx->regs + SHADOWCON);
|
|
val &= ~SHADOWCON_CHx_ENABLE(win);
|
|
val &= ~SHADOWCON_WINx_PROTECT(win);
|
|
writel(val, ctx->regs + SHADOWCON);
|
|
|
|
win_data->enabled = false;
|
|
}
|
|
|
|
static struct exynos_drm_overlay_ops fimd_overlay_ops = {
|
|
.mode_set = fimd_win_mode_set,
|
|
.commit = fimd_win_commit,
|
|
.disable = fimd_win_disable,
|
|
};
|
|
|
|
static struct exynos_drm_manager fimd_manager = {
|
|
.pipe = -1,
|
|
.ops = &fimd_manager_ops,
|
|
.overlay_ops = &fimd_overlay_ops,
|
|
.display_ops = &fimd_display_ops,
|
|
};
|
|
|
|
static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
|
|
{
|
|
struct exynos_drm_private *dev_priv = drm_dev->dev_private;
|
|
struct drm_pending_vblank_event *e, *t;
|
|
struct timeval now;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&drm_dev->event_lock, flags);
|
|
|
|
list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
|
|
base.link) {
|
|
/* if event's pipe isn't same as crtc then ignore it. */
|
|
if (crtc != e->pipe)
|
|
continue;
|
|
|
|
do_gettimeofday(&now);
|
|
e->event.sequence = 0;
|
|
e->event.tv_sec = now.tv_sec;
|
|
e->event.tv_usec = now.tv_usec;
|
|
|
|
list_move_tail(&e->base.link, &e->base.file_priv->event_list);
|
|
wake_up_interruptible(&e->base.file_priv->event_wait);
|
|
drm_vblank_put(drm_dev, crtc);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&drm_dev->event_lock, flags);
|
|
}
|
|
|
|
static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
|
|
{
|
|
struct fimd_context *ctx = (struct fimd_context *)dev_id;
|
|
struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
|
|
struct drm_device *drm_dev = subdrv->drm_dev;
|
|
struct exynos_drm_manager *manager = subdrv->manager;
|
|
u32 val;
|
|
|
|
val = readl(ctx->regs + VIDINTCON1);
|
|
|
|
if (val & VIDINTCON1_INT_FRAME)
|
|
/* VSYNC interrupt */
|
|
writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
|
|
|
|
/* check the crtc is detached already from encoder */
|
|
if (manager->pipe < 0)
|
|
goto out;
|
|
|
|
drm_handle_vblank(drm_dev, manager->pipe);
|
|
fimd_finish_pageflip(drm_dev, manager->pipe);
|
|
|
|
/* set wait vsync event to zero and wake up queue. */
|
|
if (atomic_read(&ctx->wait_vsync_event)) {
|
|
atomic_set(&ctx->wait_vsync_event, 0);
|
|
DRM_WAKEUP(&ctx->wait_vsync_queue);
|
|
}
|
|
out:
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
|
|
{
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
/*
|
|
* enable drm irq mode.
|
|
* - with irq_enabled = 1, we can use the vblank feature.
|
|
*
|
|
* P.S. note that we wouldn't use drm irq handler but
|
|
* just specific driver own one instead because
|
|
* drm framework supports only one irq handler.
|
|
*/
|
|
drm_dev->irq_enabled = 1;
|
|
|
|
/*
|
|
* with vblank_disable_allowed = 1, vblank interrupt will be disabled
|
|
* by drm timer once a current process gives up ownership of
|
|
* vblank event.(after drm_vblank_put function is called)
|
|
*/
|
|
drm_dev->vblank_disable_allowed = 1;
|
|
|
|
/* attach this sub driver to iommu mapping if supported. */
|
|
if (is_drm_iommu_supported(drm_dev))
|
|
drm_iommu_attach_device(drm_dev, dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
|
|
{
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
/* detach this sub driver from iommu mapping if supported. */
|
|
if (is_drm_iommu_supported(drm_dev))
|
|
drm_iommu_detach_device(drm_dev, dev);
|
|
}
|
|
|
|
static int fimd_calc_clkdiv(struct fimd_context *ctx,
|
|
struct fb_videomode *timing)
|
|
{
|
|
unsigned long clk = clk_get_rate(ctx->lcd_clk);
|
|
u32 retrace;
|
|
u32 clkdiv;
|
|
u32 best_framerate = 0;
|
|
u32 framerate;
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
retrace = timing->left_margin + timing->hsync_len +
|
|
timing->right_margin + timing->xres;
|
|
retrace *= timing->upper_margin + timing->vsync_len +
|
|
timing->lower_margin + timing->yres;
|
|
|
|
/* default framerate is 60Hz */
|
|
if (!timing->refresh)
|
|
timing->refresh = 60;
|
|
|
|
clk /= retrace;
|
|
|
|
for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
|
|
int tmp;
|
|
|
|
/* get best framerate */
|
|
framerate = clk / clkdiv;
|
|
tmp = timing->refresh - framerate;
|
|
if (tmp < 0) {
|
|
best_framerate = framerate;
|
|
continue;
|
|
} else {
|
|
if (!best_framerate)
|
|
best_framerate = framerate;
|
|
else if (tmp < (best_framerate - framerate))
|
|
best_framerate = framerate;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return clkdiv;
|
|
}
|
|
|
|
static void fimd_clear_win(struct fimd_context *ctx, int win)
|
|
{
|
|
u32 val;
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
writel(0, ctx->regs + WINCON(win));
|
|
writel(0, ctx->regs + VIDOSD_A(win));
|
|
writel(0, ctx->regs + VIDOSD_B(win));
|
|
writel(0, ctx->regs + VIDOSD_C(win));
|
|
|
|
if (win == 1 || win == 2)
|
|
writel(0, ctx->regs + VIDOSD_D(win));
|
|
|
|
val = readl(ctx->regs + SHADOWCON);
|
|
val &= ~SHADOWCON_WINx_PROTECT(win);
|
|
writel(val, ctx->regs + SHADOWCON);
|
|
}
|
|
|
|
static int fimd_clock(struct fimd_context *ctx, bool enable)
|
|
{
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
if (enable) {
|
|
int ret;
|
|
|
|
ret = clk_enable(ctx->bus_clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_enable(ctx->lcd_clk);
|
|
if (ret < 0) {
|
|
clk_disable(ctx->bus_clk);
|
|
return ret;
|
|
}
|
|
} else {
|
|
clk_disable(ctx->lcd_clk);
|
|
clk_disable(ctx->bus_clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fimd_window_suspend(struct device *dev)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
struct fimd_win_data *win_data;
|
|
int i;
|
|
|
|
for (i = 0; i < WINDOWS_NR; i++) {
|
|
win_data = &ctx->win_data[i];
|
|
win_data->resume = win_data->enabled;
|
|
fimd_win_disable(dev, i);
|
|
}
|
|
fimd_wait_for_vblank(dev);
|
|
}
|
|
|
|
static void fimd_window_resume(struct device *dev)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
struct fimd_win_data *win_data;
|
|
int i;
|
|
|
|
for (i = 0; i < WINDOWS_NR; i++) {
|
|
win_data = &ctx->win_data[i];
|
|
win_data->enabled = win_data->resume;
|
|
win_data->resume = false;
|
|
}
|
|
}
|
|
|
|
static int fimd_activate(struct fimd_context *ctx, bool enable)
|
|
{
|
|
struct device *dev = ctx->subdrv.dev;
|
|
if (enable) {
|
|
int ret;
|
|
|
|
ret = fimd_clock(ctx, true);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ctx->suspended = false;
|
|
|
|
/* if vblank was enabled status, enable it again. */
|
|
if (test_and_clear_bit(0, &ctx->irq_flags))
|
|
fimd_enable_vblank(dev);
|
|
|
|
fimd_window_resume(dev);
|
|
} else {
|
|
fimd_window_suspend(dev);
|
|
|
|
fimd_clock(ctx, false);
|
|
ctx->suspended = true;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit fimd_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct fimd_context *ctx;
|
|
struct exynos_drm_subdrv *subdrv;
|
|
struct exynos_drm_fimd_pdata *pdata;
|
|
struct exynos_drm_panel_info *panel;
|
|
struct resource *res;
|
|
int win;
|
|
int ret = -EINVAL;
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(dev, "no platform data specified\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
panel = &pdata->panel;
|
|
if (!panel) {
|
|
dev_err(dev, "panel is null.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
|
|
if (!ctx)
|
|
return -ENOMEM;
|
|
|
|
ctx->bus_clk = devm_clk_get(dev, "fimd");
|
|
if (IS_ERR(ctx->bus_clk)) {
|
|
dev_err(dev, "failed to get bus clock\n");
|
|
return PTR_ERR(ctx->bus_clk);
|
|
}
|
|
|
|
ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
|
|
if (IS_ERR(ctx->lcd_clk)) {
|
|
dev_err(dev, "failed to get lcd clock\n");
|
|
return PTR_ERR(ctx->lcd_clk);
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
ctx->regs = devm_request_and_ioremap(&pdev->dev, res);
|
|
if (!ctx->regs) {
|
|
dev_err(dev, "failed to map registers\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (!res) {
|
|
dev_err(dev, "irq request failed.\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ctx->irq = res->start;
|
|
|
|
ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler,
|
|
0, "drm_fimd", ctx);
|
|
if (ret) {
|
|
dev_err(dev, "irq request failed.\n");
|
|
return ret;
|
|
}
|
|
|
|
ctx->vidcon0 = pdata->vidcon0;
|
|
ctx->vidcon1 = pdata->vidcon1;
|
|
ctx->default_win = pdata->default_win;
|
|
ctx->panel = panel;
|
|
DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
|
|
atomic_set(&ctx->wait_vsync_event, 0);
|
|
|
|
subdrv = &ctx->subdrv;
|
|
|
|
subdrv->dev = dev;
|
|
subdrv->manager = &fimd_manager;
|
|
subdrv->probe = fimd_subdrv_probe;
|
|
subdrv->remove = fimd_subdrv_remove;
|
|
|
|
mutex_init(&ctx->lock);
|
|
|
|
platform_set_drvdata(pdev, ctx);
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_get_sync(dev);
|
|
|
|
ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
|
|
panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
|
|
|
|
DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
|
|
panel->timing.pixclock, ctx->clkdiv);
|
|
|
|
for (win = 0; win < WINDOWS_NR; win++)
|
|
fimd_clear_win(ctx, win);
|
|
|
|
exynos_drm_subdrv_register(subdrv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit fimd_remove(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct fimd_context *ctx = platform_get_drvdata(pdev);
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
exynos_drm_subdrv_unregister(&ctx->subdrv);
|
|
|
|
if (ctx->suspended)
|
|
goto out;
|
|
|
|
clk_disable(ctx->lcd_clk);
|
|
clk_disable(ctx->bus_clk);
|
|
|
|
pm_runtime_set_suspended(dev);
|
|
pm_runtime_put_sync(dev);
|
|
|
|
out:
|
|
pm_runtime_disable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int fimd_suspend(struct device *dev)
|
|
{
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|
struct fimd_context *ctx = get_fimd_context(dev);
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|
|
|
/*
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* do not use pm_runtime_suspend(). if pm_runtime_suspend() is
|
|
* called here, an error would be returned by that interface
|
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* because the usage_count of pm runtime is more than 1.
|
|
*/
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if (!pm_runtime_suspended(dev))
|
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return fimd_activate(ctx, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fimd_resume(struct device *dev)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
|
|
/*
|
|
* if entered to sleep when lcd panel was on, the usage_count
|
|
* of pm runtime would still be 1 so in this case, fimd driver
|
|
* should be on directly not drawing on pm runtime interface.
|
|
*/
|
|
if (pm_runtime_suspended(dev)) {
|
|
int ret;
|
|
|
|
ret = fimd_activate(ctx, true);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/*
|
|
* in case of dpms on(standby), fimd_apply function will
|
|
* be called by encoder's dpms callback to update fimd's
|
|
* registers but in case of sleep wakeup, it's not.
|
|
* so fimd_apply function should be called at here.
|
|
*/
|
|
fimd_apply(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int fimd_runtime_suspend(struct device *dev)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
return fimd_activate(ctx, false);
|
|
}
|
|
|
|
static int fimd_runtime_resume(struct device *dev)
|
|
{
|
|
struct fimd_context *ctx = get_fimd_context(dev);
|
|
|
|
DRM_DEBUG_KMS("%s\n", __FILE__);
|
|
|
|
return fimd_activate(ctx, true);
|
|
}
|
|
#endif
|
|
|
|
static struct platform_device_id fimd_driver_ids[] = {
|
|
{
|
|
.name = "exynos4-fb",
|
|
.driver_data = (unsigned long)&exynos4_fimd_driver_data,
|
|
}, {
|
|
.name = "exynos5-fb",
|
|
.driver_data = (unsigned long)&exynos5_fimd_driver_data,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
|
|
|
|
static const struct dev_pm_ops fimd_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
|
|
SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
|
|
};
|
|
|
|
struct platform_driver fimd_driver = {
|
|
.probe = fimd_probe,
|
|
.remove = __devexit_p(fimd_remove),
|
|
.id_table = fimd_driver_ids,
|
|
.driver = {
|
|
.name = "exynos4-fb",
|
|
.owner = THIS_MODULE,
|
|
.pm = &fimd_pm_ops,
|
|
},
|
|
};
|