Vivek Gautam 9bde18c1b5 phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support ... Exynos7 SoC has now separate gate control for 125MHz pipe3 phy clock, as well as 60MHz utmi phy clock. Additionally, separate gate control is available for the clock used for ITP (Isochronous Transfer Packet) generation. So get the same and control in the phy-exynos5-usbdrd driver. Suggested-by: Anton Tikhomirov <av.tikhomirov@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>		2014-11-22 14:08:09 +05:30
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bindings	phy: exynos5-usbdrd: Add pipe-clk, utmi-clk and itp-clk support	2014-11-22 14:08:09 +05:30
00-INDEX	Documentation/: update 00-INDEX files	2014-02-10 16:01:40 -08:00
booting-without-of.txt	dt/documentation: add specification of dma bus information	2014-09-26 11:18:05 -05:00
changesets.txt	of: Transactional DT support.	2014-07-23 17:29:15 -06:00
dynamic-resolution-notes.txt	of: Introduce Device Tree resolve support.	2014-10-04 21:24:26 +01:00
of_selftest.txt	To remove non-ascii characters in of_selftest.txt	2014-10-06 09:52:39 +01:00
todo.txt	of: Add todo tasklist for Devicetree	2014-07-23 17:33:01 -06:00
usage-model.txt	…