2956f36c95
Update DMA address index instead of allocating new sg list to impose 2k size limit for each entry. Signed-off-by: Harsh Jain <harsh@chelsio.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
101 lines
3 KiB
C
101 lines
3 KiB
C
/*
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* This file is part of the Chelsio T6 Crypto driver for Linux.
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*
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* Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef __CHCR_CORE_H__
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#define __CHCR_CORE_H__
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#include <crypto/algapi.h>
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#include "t4_hw.h"
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#include "cxgb4.h"
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#include "cxgb4_uld.h"
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#define DRV_MODULE_NAME "chcr"
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#define DRV_VERSION "1.0.0.0"
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#define MAX_PENDING_REQ_TO_HW 20
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#define CHCR_TEST_RESPONSE_TIMEOUT 1000
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#define PAD_ERROR_BIT 1
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#define CHK_PAD_ERR_BIT(x) (((x) >> PAD_ERROR_BIT) & 1)
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#define MAC_ERROR_BIT 0
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#define CHK_MAC_ERR_BIT(x) (((x) >> MAC_ERROR_BIT) & 1)
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#define MAX_SALT 4
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#define WR_MIN_LEN (sizeof(struct chcr_wr) + \
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sizeof(struct cpl_rx_phys_dsgl) + \
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sizeof(struct ulptx_sgl))
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#define padap(dev) pci_get_drvdata(dev->u_ctx->lldi.pdev)
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struct uld_ctx;
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struct _key_ctx {
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__be32 ctx_hdr;
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u8 salt[MAX_SALT];
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__be64 reserverd;
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unsigned char key[0];
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};
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struct chcr_wr {
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struct fw_crypto_lookaside_wr wreq;
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struct ulp_txpkt ulptx;
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struct ulptx_idata sc_imm;
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struct cpl_tx_sec_pdu sec_cpl;
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struct _key_ctx key_ctx;
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};
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struct chcr_dev {
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spinlock_t lock_chcr_dev;
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struct uld_ctx *u_ctx;
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unsigned char tx_channel_id;
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unsigned char rx_channel_id;
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};
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struct uld_ctx {
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struct list_head entry;
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struct cxgb4_lld_info lldi;
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struct chcr_dev *dev;
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};
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struct uld_ctx *assign_chcr_device(void);
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int chcr_send_wr(struct sk_buff *skb);
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int start_crypto(void);
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int stop_crypto(void);
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int chcr_uld_rx_handler(void *handle, const __be64 *rsp,
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const struct pkt_gl *pgl);
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int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
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int err);
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#endif /* __CHCR_CORE_H__ */
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