b3a5af435a
This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - Cleanups for Renesas shmobile platforms - Lots of added devices on LPC18xx - Lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz 9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz 8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a dYwdms39p6AIT43rK+m3 =D2Pm -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
710 lines
17 KiB
Plaintext
710 lines
17 KiB
Plaintext
/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra74x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "TI DRA742";
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x60000000>; /* 1536 MB */
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};
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evm_3v3_sd: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
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};
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mmc2_3v3: fixedregulator-mmc2 {
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compatible = "regulator-fixed";
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regulator-name = "mmc2_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb2: extcon_usb2 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
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};
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vtt_fixed: fixedregulator-vtt {
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compatible = "regulator-fixed";
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regulator-name = "vtt_fixed";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-boot-on;
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enable-active-high;
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gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
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};
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};
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&dra7_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <&vtt_pin>;
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vtt_pin: pinmux_vtt_pin {
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pinctrl-single,pins = <
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0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
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0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
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>;
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};
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i2c2_pins: pinmux_i2c2_pins {
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pinctrl-single,pins = <
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0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
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0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
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>;
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};
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i2c3_pins: pinmux_i2c3_pins {
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pinctrl-single,pins = <
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0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
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0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
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>;
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};
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mcspi1_pins: pinmux_mcspi1_pins {
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pinctrl-single,pins = <
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0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
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0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
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0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
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0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
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0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
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0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
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>;
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};
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mcspi2_pins: pinmux_mcspi2_pins {
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pinctrl-single,pins = <
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0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
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0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
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0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
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0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
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0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
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0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
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>;
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};
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uart2_pins: pinmux_uart2_pins {
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pinctrl-single,pins = <
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0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
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0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
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0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
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0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
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0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
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>;
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};
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qspi1_pins: pinmux_qspi1_pins {
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pinctrl-single,pins = <
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0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
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0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
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0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
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0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
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0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
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0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
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0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
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0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
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0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
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0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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>;
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};
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usb2_pins: pinmux_usb2_pins {
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pinctrl-single,pins = <
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0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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nand_flash_x16: nand_flash_x16 {
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/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
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* So NAND flash requires following switch settings:
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* SW5.9 (GPMC_WPN) = LOW
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* SW5.1 (NAND_BOOTn) = HIGH */
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pinctrl-single,pins = <
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0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
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0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
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0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
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0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
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0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
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0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
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0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
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0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
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0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
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0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
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0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
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0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
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0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
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0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
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/* Slave 2 */
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0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
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0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
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0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
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0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
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0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
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0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
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0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
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0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
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0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
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0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
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0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
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0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x250 (MUX_MODE15)
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0x254 (MUX_MODE15)
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0x258 (MUX_MODE15)
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0x25c (MUX_MODE15)
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0x260 (MUX_MODE15)
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0x264 (MUX_MODE15)
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0x268 (MUX_MODE15)
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0x26c (MUX_MODE15)
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0x270 (MUX_MODE15)
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0x274 (MUX_MODE15)
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0x278 (MUX_MODE15)
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0x27c (MUX_MODE15)
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/* Slave 2 */
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0x198 (MUX_MODE15)
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0x19c (MUX_MODE15)
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0x1a0 (MUX_MODE15)
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0x1a4 (MUX_MODE15)
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0x1a8 (MUX_MODE15)
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0x1ac (MUX_MODE15)
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0x1b0 (MUX_MODE15)
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0x1b4 (MUX_MODE15)
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0x1b8 (MUX_MODE15)
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0x1bc (MUX_MODE15)
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0x1c0 (MUX_MODE15)
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0x1c4 (MUX_MODE15)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
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0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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0x23c (MUX_MODE15)
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0x240 (MUX_MODE15)
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>;
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};
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
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0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
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>;
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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tps659038: tps659038@58 {
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compatible = "ti,tps659038";
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reg = <0x58>;
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tps659038_pmic {
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compatible = "ti,tps659038-pmic";
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regulators {
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smps123_reg: smps123 {
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/* VDD_MPU */
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regulator-name = "smps123";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps45_reg: smps45 {
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/* VDD_DSPEVE */
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regulator-name = "smps45";
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regulator-min-microvolt = < 850000>;
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regulator-max-microvolt = <1150000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps6_reg: smps6 {
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/* VDD_GPU - over VDD_SMPS6 */
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regulator-name = "smps6";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps7_reg: smps7 {
|
|
/* CORE_VDD */
|
|
regulator-name = "smps7";
|
|
regulator-min-microvolt = <850000>;
|
|
regulator-max-microvolt = <1060000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps8_reg: smps8 {
|
|
/* VDD_IVAHD */
|
|
regulator-name = "smps8";
|
|
regulator-min-microvolt = < 850000>;
|
|
regulator-max-microvolt = <1250000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
smps9_reg: smps9 {
|
|
/* VDDS1V8 */
|
|
regulator-name = "smps9";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo1_reg: ldo1 {
|
|
/* LDO1_OUT --> SDIO */
|
|
regulator-name = "ldo1";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo2_reg: ldo2 {
|
|
/* VDD_RTCIO */
|
|
/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
|
|
regulator-name = "ldo2";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo3_reg: ldo3 {
|
|
/* VDDA_1V8_PHY */
|
|
regulator-name = "ldo3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo9_reg: ldo9 {
|
|
/* VDD_RTC */
|
|
regulator-name = "ldo9";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldoln_reg: ldoln {
|
|
/* VDDA_1V8_PLL */
|
|
regulator-name = "ldoln";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldousb_reg: ldousb {
|
|
/* VDDA_3V_USB: VDDA_USBHS33 */
|
|
regulator-name = "ldousb";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pcf_gpio_21: gpio@21 {
|
|
compatible = "ti,pcf8575";
|
|
reg = <0x21>;
|
|
lines-initial-states = <0x1408>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-parent = <&gpio6>;
|
|
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&i2c3 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_pins>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
&mcspi1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcspi1_pins>;
|
|
};
|
|
|
|
&mcspi2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mcspi2_pins>;
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_pins>;
|
|
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&dra7_pmx_core 0x3e0>;
|
|
};
|
|
|
|
&uart2 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_pins>;
|
|
};
|
|
|
|
&uart3 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_pins>;
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&evm_3v3_sd>;
|
|
vmmc_aux-supply = <&ldo1_reg>;
|
|
bus-width = <4>;
|
|
/*
|
|
* SDCD signal is not being used here - using the fact that GPIO mode
|
|
* is always hardwired.
|
|
*/
|
|
cd-gpios = <&gpio6 27 0>;
|
|
};
|
|
|
|
&mmc2 {
|
|
status = "okay";
|
|
vmmc-supply = <&mmc2_3v3>;
|
|
bus-width = <8>;
|
|
};
|
|
|
|
&cpu0 {
|
|
cpu0-supply = <&smps123_reg>;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi1_pins>;
|
|
|
|
spi-max-frequency = <48000000>;
|
|
m25p80@0 {
|
|
compatible = "s25fl256s1";
|
|
spi-max-frequency = <48000000>;
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-cpol;
|
|
spi-cpha;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first four physical blocks
|
|
* for a valid file to boot and the flash here is
|
|
* 64KiB block size.
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.SPL";
|
|
reg = <0x00000000 0x000010000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.SPL.backup1";
|
|
reg = <0x00010000 0x00010000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.SPL.backup2";
|
|
reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00080000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x001c0000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x001d0000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001e0000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009e0000 0x01620000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&omap_dwc3_1 {
|
|
extcon = <&extcon_usb1>;
|
|
};
|
|
|
|
&omap_dwc3_2 {
|
|
extcon = <&extcon_usb2>;
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb1_pins>;
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb2_pins>;
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_flash_x16>;
|
|
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
|
nand@0,0 {
|
|
reg = <0 0 4>; /* device IO registers */
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <16>;
|
|
gpmc,device-width = <2>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <80>;
|
|
gpmc,cs-wr-off-ns = <80>;
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <60>;
|
|
gpmc,adv-wr-off-ns = <60>;
|
|
gpmc,we-on-ns = <10>;
|
|
gpmc,we-off-ns = <50>;
|
|
gpmc,oe-on-ns = <4>;
|
|
gpmc,oe-off-ns = <40>;
|
|
gpmc,access-ns = <40>;
|
|
gpmc,wr-access-ns = <80>;
|
|
gpmc,rd-cycle-ns = <80>;
|
|
gpmc,wr-cycle-ns = <80>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wait-monitoring-ns = <0>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x000020000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
phy-supply = <&ldousb_reg>;
|
|
};
|
|
|
|
&gpio7 {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle-on-init;
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
dual_emac;
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy_id = <&davinci_mdio>, <2>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <1>;
|
|
};
|
|
|
|
&cpsw_emac1 {
|
|
phy_id = <&davinci_mdio>, <3>;
|
|
phy-mode = "rgmii";
|
|
dual_emac_res_vlan = <2>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
};
|
|
|
|
&dcan1 {
|
|
status = "ok";
|
|
pinctrl-names = "default", "sleep", "active";
|
|
pinctrl-0 = <&dcan1_pins_sleep>;
|
|
pinctrl-1 = <&dcan1_pins_sleep>;
|
|
pinctrl-2 = <&dcan1_pins_default>;
|
|
};
|