c07f827011
The dtc compiler combines all the defined nodes that have the same path so a device node definition can be in one file and later be extended in another one. That's the case of the Exynos5420 pinctrl device nodes that are defined in the exynos5420.dtsi file and extended in exynos5420-pinctrl.dtsi. But since the exynos5420.dtsi file includes the exynos5420-pinctrl.dtsi before the pinctrl device nodes are actually defined, the definition of the pinctrl device nodes happens in exynos5420-pinctrl.dtsi and are extended in exynos5420.dtsi. That is the opposite of the original intention so even when there is no difference in practice, the exynos5420-pinctrl.dtsi include should be moved at the end of the exynos5420.dtsi file after the pinctrl device nodes have been already defined. This will also allow to later change the exynos5420-pinctrl.dtsi file to use labels instead of full paths to extend the pinctrl nodes. Since keeping the include at the top, would cause a dtc build error due the pinctrl labels not being defined yet. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
1170 lines
29 KiB
Plaintext
1170 lines
29 KiB
Plaintext
/*
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* SAMSUNG EXYNOS5420 SoC device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
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* EXYNOS5420 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/exynos5420.h>
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#include "exynos5.dtsi"
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#include <dt-bindings/clock/exynos-audss-clk.h>
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/ {
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compatible = "samsung,exynos5420", "samsung,exynos5";
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aliases {
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mshc0 = &mmc_0;
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mshc1 = &mmc_1;
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mshc2 = &mmc_2;
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &hsi2c_4;
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i2c5 = &hsi2c_5;
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i2c6 = &hsi2c_6;
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i2c7 = &hsi2c_7;
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i2c8 = &hsi2c_8;
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i2c9 = &hsi2c_9;
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i2c10 = &hsi2c_10;
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gsc0 = &gsc_0;
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gsc1 = &gsc_1;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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usbdrdphy0 = &usbdrd_phy0;
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usbdrdphy1 = &usbdrd_phy1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x2>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x3>;
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clock-frequency = <1800000000>;
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cci-control-port = <&cci_control1>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <1000000000>;
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cci-control-port = <&cci_control0>;
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};
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};
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cci: cci@10d20000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10d20000 0x1000>;
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ranges = <0x0 0x10d20000 0x6000>;
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cci_control0: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control1: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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};
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x54000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x54000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@53000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x53000 0x1000>;
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};
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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clock_audss: audss-clock-controller@3810000 {
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
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<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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};
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mfc: codec@11000000 {
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compatible = "samsung,mfc-v7";
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reg = <0x11000000 0x10000>;
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interrupts = <0 96 0>;
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clocks = <&clock CLK_MFC>;
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clock-names = "mfc";
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power-domains = <&mfc_pd>;
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iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
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iommu-names = "left", "right";
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};
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mmc_0: mmc@12200000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12200000 0x2000>;
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clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_1: mmc@12210000 {
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compatible = "samsung,exynos5420-dw-mshc-smu";
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interrupts = <0 76 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12210000 0x2000>;
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clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mmc_2: mmc@12220000 {
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compatible = "samsung,exynos5420-dw-mshc";
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interrupts = <0 77 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x12220000 0x1000>;
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clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x40>;
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status = "disabled";
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};
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mct: mct@101C0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x101C0000 0x800>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &combiner 23 3>,
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<1 &combiner 23 4>,
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<2 &combiner 25 2>,
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<3 &combiner 25 3>,
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<4 &gic 0 120 0>,
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<5 &gic 0 121 0>,
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<6 &gic 0 122 0>,
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<7 &gic 0 123 0>,
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<8 &gic 0 128 0>,
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<9 &gic 0 129 0>,
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<10 &gic 0 130 0>,
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<11 &gic 0 131 0>;
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};
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};
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gsc_pd: power-domain@10044000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044000 0x20>;
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#power-domain-cells = <0>;
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clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
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clock-names = "asb0", "asb1";
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};
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isp_pd: power-domain@10044020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044020 0x20>;
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#power-domain-cells = <0>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
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clock-names = "oscclk", "clk0";
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#power-domain-cells = <0>;
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};
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msc_pd: power-domain@10044120 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044120 0x20>;
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#power-domain-cells = <0>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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#power-domain-cells = <0>;
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clocks = <&clock CLK_FIN_PLL>,
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<&clock CLK_MOUT_USER_ACLK200_DISP1>,
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<&clock CLK_MOUT_USER_ACLK300_DISP1>,
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<&clock CLK_MOUT_USER_ACLK400_DISP1>,
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<&clock CLK_FIMD1>, <&clock CLK_MIXER>;
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clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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interrupts = <0 45 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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pinctrl_1: pinctrl@13410000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13410000 0x1000>;
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interrupts = <0 78 0>;
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};
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pinctrl_2: pinctrl@14000000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14000000 0x1000>;
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interrupts = <0 46 0>;
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};
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pinctrl_3: pinctrl@14010000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x14010000 0x1000>;
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interrupts = <0 50 0>;
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};
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pinctrl_4: pinctrl@03860000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <0 47 0>;
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges;
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adma: adma@03880000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x03880000 0x1000>;
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interrupts = <0 110 0>;
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clocks = <&clock_audss EXYNOS_ADMA>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <6>;
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#dma-requests = <16>;
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};
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pdma0: pdma@121A0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121A0000 0x1000>;
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interrupts = <0 34 0>;
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clocks = <&clock CLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@121B0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x121B0000 0x1000>;
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interrupts = <0 35 0>;
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clocks = <&clock CLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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mdma0: mdma@10800000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x10800000 0x1000>;
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interrupts = <0 33 0>;
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clocks = <&clock CLK_MDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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};
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mdma1: mdma@11C10000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x11C10000 0x1000>;
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interrupts = <0 124 0>;
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clocks = <&clock CLK_MDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <1>;
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/*
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* MDMA1 can support both secure and non-secure
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* AXI transactions. When this is enabled in the kernel
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* for boards that run in secure mode, we are getting
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* imprecise external aborts causing the kernel to oops.
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*/
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status = "disabled";
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};
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};
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i2s0: i2s@03830000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x03830000 0x100>;
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dmas = <&adma 0
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&adma 2
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&adma 1>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk0";
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#sound-dai-cells = <1>;
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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status = "disabled";
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};
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i2s1: i2s@12D60000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x12D60000 0x100>;
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dmas = <&pdma1 12
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&pdma1 11>;
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dma-names = "tx", "rx";
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clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
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clock-names = "iis", "i2s_opclk0";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk1";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s2: i2s@12D70000 {
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compatible = "samsung,exynos5420-i2s";
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reg = <0x12D70000 0x100>;
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dmas = <&pdma0 12
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&pdma0 11>;
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dma-names = "tx", "rx";
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clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
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clock-names = "iis", "i2s_opclk0";
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#clock-cells = <1>;
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clock-output-names = "i2s_cdclk2";
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#sound-dai-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s2_bus>;
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status = "disabled";
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};
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spi_0: spi@12d20000 {
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compatible = "samsung,exynos4210-spi";
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reg = <0x12d20000 0x100>;
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interrupts = <0 68 0>;
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dmas = <&pdma0 5
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&pdma0 4>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_bus>;
|
|
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@12d30000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d30000 0x100>;
|
|
interrupts = <0 69 0>;
|
|
dmas = <&pdma1 5
|
|
&pdma1 4>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@12d40000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x12d40000 0x100>;
|
|
interrupts = <0 70 0>;
|
|
dmas = <&pdma0 7
|
|
&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@12dd0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x12dd0000 0x100>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock CLK_PWM>;
|
|
clock-names = "timers";
|
|
};
|
|
|
|
dp_phy: video-phy@10040728 {
|
|
compatible = "samsung,exynos5420-dp-video-phy";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
mipi_phy: video-phy@10040714 {
|
|
compatible = "samsung,s5pv210-mipi-video-phy";
|
|
syscon = <&pmu_system_controller>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
dsi@14500000 {
|
|
compatible = "samsung,exynos5410-mipi-dsi";
|
|
reg = <0x14500000 0x10000>;
|
|
interrupts = <0 82 0>;
|
|
phys = <&mipi_phy 1>;
|
|
phy-names = "dsim";
|
|
clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
|
|
clock-names = "bus_clk", "pll_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc: adc@12D10000 {
|
|
compatible = "samsung,exynos-adc-v2";
|
|
reg = <0x12D10000 0x100>;
|
|
interrupts = <0 106 0>;
|
|
clocks = <&clock CLK_TSADC>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_0: i2c@12C60000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C60000 0x100>;
|
|
interrupts = <0 56 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C0>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_bus>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_1: i2c@12C70000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C70000 0x100>;
|
|
interrupts = <0 57 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C1>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_2: i2c@12C80000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C80000 0x100>;
|
|
interrupts = <0 58 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C2>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_3: i2c@12C90000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x12C90000 0x100>;
|
|
interrupts = <0 59 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_4: i2c@12CA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CA0000 0x1000>;
|
|
interrupts = <0 60 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_hs_bus>;
|
|
clocks = <&clock CLK_USI0>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_5: i2c@12CB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CB0000 0x1000>;
|
|
interrupts = <0 61 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_hs_bus>;
|
|
clocks = <&clock CLK_USI1>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_6: i2c@12CC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CC0000 0x1000>;
|
|
interrupts = <0 62 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_hs_bus>;
|
|
clocks = <&clock CLK_USI2>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_7: i2c@12CD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12CD0000 0x1000>;
|
|
interrupts = <0 63 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_hs_bus>;
|
|
clocks = <&clock CLK_USI3>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_8: i2c@12E00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E00000 0x1000>;
|
|
interrupts = <0 87 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8_hs_bus>;
|
|
clocks = <&clock CLK_USI4>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_9: i2c@12E10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E10000 0x1000>;
|
|
interrupts = <0 88 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c9_hs_bus>;
|
|
clocks = <&clock CLK_USI5>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsi2c_10: i2c@12E20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
reg = <0x12E20000 0x1000>;
|
|
interrupts = <0 203 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c10_hs_bus>;
|
|
clocks = <&clock CLK_USI6>;
|
|
clock-names = "hsi2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@14530000 {
|
|
compatible = "samsung,exynos5420-hdmi";
|
|
reg = <0x14530000 0x70000>;
|
|
interrupts = <0 95 0>;
|
|
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
|
|
<&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
|
|
<&clock CLK_MOUT_HDMI>;
|
|
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
|
|
"sclk_hdmiphy", "mout_hdmi";
|
|
phy = <&hdmiphy>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
power-domains = <&disp_pd>;
|
|
};
|
|
|
|
hdmiphy: hdmiphy@145D0000 {
|
|
reg = <0x145D0000 0x20>;
|
|
};
|
|
|
|
mixer: mixer@14450000 {
|
|
compatible = "samsung,exynos5420-mixer";
|
|
reg = <0x14450000 0x10000>;
|
|
interrupts = <0 94 0>;
|
|
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
|
|
<&clock CLK_SCLK_HDMI>;
|
|
clock-names = "mixer", "hdmi", "sclk_hdmi";
|
|
power-domains = <&disp_pd>;
|
|
iommus = <&sysmmu_tv>;
|
|
};
|
|
|
|
gsc_0: video-scaler@13e00000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e00000 0x1000>;
|
|
interrupts = <0 85 0>;
|
|
clocks = <&clock CLK_GSCL0>;
|
|
clock-names = "gscl";
|
|
power-domains = <&gsc_pd>;
|
|
iommus = <&sysmmu_gscl0>;
|
|
};
|
|
|
|
gsc_1: video-scaler@13e10000 {
|
|
compatible = "samsung,exynos5-gsc";
|
|
reg = <0x13e10000 0x1000>;
|
|
interrupts = <0 86 0>;
|
|
clocks = <&clock CLK_GSCL1>;
|
|
clock-names = "gscl";
|
|
power-domains = <&gsc_pd>;
|
|
iommus = <&sysmmu_gscl1>;
|
|
};
|
|
|
|
jpeg_0: jpeg@11F50000 {
|
|
compatible = "samsung,exynos5420-jpeg";
|
|
reg = <0x11F50000 0x1000>;
|
|
interrupts = <0 89 0>;
|
|
clock-names = "jpeg";
|
|
clocks = <&clock CLK_JPEG>;
|
|
iommus = <&sysmmu_jpeg0>;
|
|
};
|
|
|
|
jpeg_1: jpeg@11F60000 {
|
|
compatible = "samsung,exynos5420-jpeg";
|
|
reg = <0x11F60000 0x1000>;
|
|
interrupts = <0 168 0>;
|
|
clock-names = "jpeg";
|
|
clocks = <&clock CLK_JPEG2>;
|
|
iommus = <&sysmmu_jpeg1>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@10040000 {
|
|
compatible = "samsung,exynos5420-pmu", "syscon";
|
|
reg = <0x10040000 0x5000>;
|
|
clock-names = "clkout16";
|
|
clocks = <&clock CLK_FIN_PLL>;
|
|
#clock-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
sysreg_system_controller: syscon@10050000 {
|
|
compatible = "samsung,exynos5-sysreg", "syscon";
|
|
reg = <0x10050000 0x5000>;
|
|
};
|
|
|
|
tmu_cpu0: tmu@10060000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10060000 0x100>;
|
|
interrupts = <0 65 0>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
tmu_cpu1: tmu@10064000 {
|
|
compatible = "samsung,exynos5420-tmu";
|
|
reg = <0x10064000 0x100>;
|
|
interrupts = <0 183 0>;
|
|
clocks = <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif";
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
tmu_cpu2: tmu@10068000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
|
interrupts = <0 184 0>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
tmu_cpu3: tmu@1006c000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
|
interrupts = <0 185 0>;
|
|
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
tmu_gpu: tmu@100a0000 {
|
|
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
|
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
|
interrupts = <0 215 0>;
|
|
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
|
|
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
|
#include "exynos4412-tmu-sensor-conf.dtsi"
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu0_thermal: cpu0-thermal {
|
|
thermal-sensors = <&tmu_cpu0>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu1_thermal: cpu1-thermal {
|
|
thermal-sensors = <&tmu_cpu1>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu2_thermal: cpu2-thermal {
|
|
thermal-sensors = <&tmu_cpu2>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
cpu3_thermal: cpu3-thermal {
|
|
thermal-sensors = <&tmu_cpu3>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
gpu_thermal: gpu-thermal {
|
|
thermal-sensors = <&tmu_gpu>;
|
|
#include "exynos5420-trip-points.dtsi"
|
|
};
|
|
};
|
|
|
|
watchdog: watchdog@101D0000 {
|
|
compatible = "samsung,exynos5420-wdt";
|
|
reg = <0x101D0000 0x100>;
|
|
interrupts = <0 42 0>;
|
|
clocks = <&clock CLK_WDT>;
|
|
clock-names = "watchdog";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
sss: sss@10830000 {
|
|
compatible = "samsung,exynos4210-secss";
|
|
reg = <0x10830000 0x10000>;
|
|
interrupts = <0 112 0>;
|
|
clocks = <&clock CLK_SSS>;
|
|
clock-names = "secss";
|
|
};
|
|
|
|
usbdrd3_0: usb@12000000 {
|
|
compatible = "samsung,exynos5250-dwusb3";
|
|
clocks = <&clock CLK_USBD300>;
|
|
clock-names = "usbdrd30";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
usbdrd_dwc3_0: dwc3 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x12000000 0x10000>;
|
|
interrupts = <0 72 0>;
|
|
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usbdrd_phy0: phy@12100000 {
|
|
compatible = "samsung,exynos5420-usbdrd-phy";
|
|
reg = <0x12100000 0x100>;
|
|
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
|
|
clock-names = "phy", "ref";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
usbdrd3_1: usb@12400000 {
|
|
compatible = "samsung,exynos5250-dwusb3";
|
|
clocks = <&clock CLK_USBD301>;
|
|
clock-names = "usbdrd30";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
usbdrd_dwc3_1: dwc3 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x12400000 0x10000>;
|
|
interrupts = <0 73 0>;
|
|
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usbdrd_phy1: phy@12500000 {
|
|
compatible = "samsung,exynos5420-usbdrd-phy";
|
|
reg = <0x12500000 0x100>;
|
|
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
|
|
clock-names = "phy", "ref";
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
usbhost2: usb@12110000 {
|
|
compatible = "samsung,exynos4210-ehci";
|
|
reg = <0x12110000 0x100>;
|
|
interrupts = <0 71 0>;
|
|
|
|
clocks = <&clock CLK_USBH20>;
|
|
clock-names = "usbhost";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
phys = <&usb2_phy 1>;
|
|
};
|
|
};
|
|
|
|
usbhost1: usb@12120000 {
|
|
compatible = "samsung,exynos4210-ohci";
|
|
reg = <0x12120000 0x100>;
|
|
interrupts = <0 71 0>;
|
|
|
|
clocks = <&clock CLK_USBH20>;
|
|
clock-names = "usbhost";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
phys = <&usb2_phy 1>;
|
|
};
|
|
};
|
|
|
|
usb2_phy: phy@12130000 {
|
|
compatible = "samsung,exynos5250-usb2-phy";
|
|
reg = <0x12130000 0x100>;
|
|
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
|
|
clock-names = "phy", "ref";
|
|
#phy-cells = <1>;
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
samsung,pmureg-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
sysmmu_g2dr: sysmmu@0x10A60000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x10A60000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <24 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_g2dw: sysmmu@0x10A70000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x10A70000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_tv: sysmmu@0x14650000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14650000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <7 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_gscl0: sysmmu@0x13E80000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E80000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
|
|
power-domains = <&gsc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_gscl1: sysmmu@0x13E90000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x13E90000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
|
|
power-domains = <&gsc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler0r: sysmmu@0x12880000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12880000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 4>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler1r: sysmmu@0x12890000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x12890000 0x1000>;
|
|
interrupts = <0 186 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler2r: sysmmu@0x128A0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128A0000 0x1000>;
|
|
interrupts = <0 188 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler0w: sysmmu@0x128C0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128C0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <27 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler1w: sysmmu@0x128D0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128D0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <22 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_scaler2w: sysmmu@0x128E0000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x128E0000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <19 6>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_jpeg0: sysmmu@0x11F10000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11F10000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <4 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_jpeg1: sysmmu@0x11F20000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11F20000 0x1000>;
|
|
interrupts = <0 169 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_mfc_l: sysmmu@0x11200000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11200000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <6 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
|
|
power-domains = <&mfc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_mfc_r: sysmmu@0x11210000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x11210000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <8 5>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
|
|
power-domains = <&mfc_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimd1_0: sysmmu@0x14640000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14640000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <3 2>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
|
|
sysmmu_fimd1_1: sysmmu@0x14680000 {
|
|
compatible = "samsung,exynos-sysmmu";
|
|
reg = <0x14680000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <3 0>;
|
|
clock-names = "sysmmu", "master";
|
|
clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
|
|
power-domains = <&disp_pd>;
|
|
#iommu-cells = <0>;
|
|
};
|
|
};
|
|
|
|
&dp {
|
|
clocks = <&clock CLK_DP1>;
|
|
clock-names = "dp";
|
|
phys = <&dp_phy>;
|
|
phy-names = "dp";
|
|
power-domains = <&disp_pd>;
|
|
};
|
|
|
|
&fimd {
|
|
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
|
|
clock-names = "sclk_fimd", "fimd";
|
|
power-domains = <&disp_pd>;
|
|
iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
|
|
iommu-names = "m0", "m1";
|
|
};
|
|
|
|
&rtc {
|
|
clocks = <&clock CLK_RTC>;
|
|
clock-names = "rtc";
|
|
interrupt-parent = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
&serial_0 {
|
|
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
&serial_1 {
|
|
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
&serial_2 {
|
|
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
&serial_3 {
|
|
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
|
|
clock-names = "uart", "clk_uart_baud0";
|
|
};
|
|
|
|
#include "exynos5420-pinctrl.dtsi"
|