b3a5af435a
This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - Cleanups for Renesas shmobile platforms - Lots of added devices on LPC18xx - Lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz 9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz 8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a dYwdms39p6AIT43rK+m3 =D2Pm -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
1264 lines
35 KiB
Plaintext
1264 lines
35 KiB
Plaintext
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/imx6sx-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx6sx-pinfunc.h"
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#include "skeleton.dtsi"
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/ {
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aliases {
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can0 = &flexcan1;
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can1 = &flexcan2;
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mmc3 = &usdhc4;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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spi4 = &ecspi5;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1075000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6SX_CLK_ARM>,
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<&clks IMX6SX_CLK_PLL2_PFD2>,
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<&clks IMX6SX_CLK_STEP>,
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<&clks IMX6SX_CLK_PLL1_SW>,
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<&clks IMX6SX_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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};
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};
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intc: interrupt-controller@00a01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00a01000 0x1000>,
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<0x00a00100 0x100>;
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interrupt-parent = <&intc>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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ckil: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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};
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osc: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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};
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ipp_di0: clock@2 {
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compatible = "fixed-clock";
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reg = <2>;
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di0";
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};
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ipp_di1: clock@3 {
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compatible = "fixed-clock";
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reg = <3>;
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di1";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gpc>;
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ranges;
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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clocks = <&clks IMX6SX_CLK_OCRAM>;
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};
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L2: l2-cache@00a02000 {
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compatible = "arm,pl310-cache";
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reg = <0x00a02000 0x1000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <4 2 3>;
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arm,data-latency = <4 2 3>;
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};
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dma_apbh: dma-apbh@01804000 {
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compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x01804000 0x2000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clks IMX6SX_CLK_APBH_DMA>;
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};
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gpmi: gpmi-nand@01806000{
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compatible = "fsl,imx6sx-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&clks IMX6SX_CLK_GPMI_IO>,
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<&clks IMX6SX_CLK_GPMI_APB>,
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<&clks IMX6SX_CLK_GPMI_BCH>,
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<&clks IMX6SX_CLK_GPMI_BCH_APB>,
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<&clks IMX6SX_CLK_PER1_BCH>;
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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aips1: aips-bus@02000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x100000>;
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ranges;
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spba-bus@02000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x40000>;
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ranges;
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spdif: spdif@02004000 {
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compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks IMX6SX_CLK_SPDIF>,
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<&clks IMX6SX_CLK_OSC>,
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<&clks IMX6SX_CLK_SPDIF>,
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<&clks 0>, <&clks 0>, <&clks 0>,
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<&clks IMX6SX_CLK_IPG>,
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<&clks 0>, <&clks 0>,
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<&clks IMX6SX_CLK_SPBA>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7", "dma";
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status = "disabled";
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};
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ecspi1: ecspi@02008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
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reg = <0x02008000 0x4000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ECSPI1>,
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<&clks IMX6SX_CLK_ECSPI1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi2: ecspi@0200c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
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reg = <0x0200c000 0x4000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ECSPI2>,
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<&clks IMX6SX_CLK_ECSPI2>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi3: ecspi@02010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
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reg = <0x02010000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ECSPI3>,
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<&clks IMX6SX_CLK_ECSPI3>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi4: ecspi@02014000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
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reg = <0x02014000 0x4000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ECSPI4>,
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<&clks IMX6SX_CLK_ECSPI4>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@02020000 {
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compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_UART_IPG>,
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<&clks IMX6SX_CLK_UART_SERIAL>;
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clock-names = "ipg", "per";
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dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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esai: esai@02024000 {
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reg = <0x02024000 0x4000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
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<&clks IMX6SX_CLK_ESAI_MEM>,
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<&clks IMX6SX_CLK_ESAI_EXTAL>,
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<&clks IMX6SX_CLK_ESAI_IPG>,
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<&clks IMX6SX_CLK_SPBA>;
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clock-names = "core", "mem", "extal",
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"fsys", "dma";
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status = "disabled";
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};
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ssi1: ssi@02028000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
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reg = <0x02028000 0x4000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
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<&clks IMX6SX_CLK_SSI1>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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ssi2: ssi@0202c000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
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reg = <0x0202c000 0x4000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
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<&clks IMX6SX_CLK_SSI2>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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ssi3: ssi@02030000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
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reg = <0x02030000 0x4000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
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<&clks IMX6SX_CLK_SSI3>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <15>;
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status = "disabled";
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};
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asrc: asrc@02034000 {
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reg = <0x02034000 0x4000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
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<&clks IMX6SX_CLK_ASRC_IPG>,
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<&clks IMX6SX_CLK_SPDIF>,
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<&clks IMX6SX_CLK_SPBA>;
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clock-names = "mem", "ipg", "asrck", "dma";
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dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
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<&sdma 19 20 1>, <&sdma 20 20 1>,
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<&sdma 21 20 1>, <&sdma 22 20 1>;
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dma-names = "rxa", "rxb", "rxc",
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"txa", "txb", "txc";
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status = "okay";
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};
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};
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pwm1: pwm@02080000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x02080000 0x4000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6SX_CLK_PWM1>,
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<&clks IMX6SX_CLK_PWM1>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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};
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pwm2: pwm@02084000 {
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compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
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reg = <0x02084000 0x4000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM2>,
|
|
<&clks IMX6SX_CLK_PWM2>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pwm3: pwm@02088000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02088000 0x4000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM3>,
|
|
<&clks IMX6SX_CLK_PWM3>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pwm4: pwm@0208c000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x0208c000 0x4000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM4>,
|
|
<&clks IMX6SX_CLK_PWM4>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
flexcan1: can@02090000 {
|
|
compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x02090000 0x4000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
|
|
<&clks IMX6SX_CLK_CAN1_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan2: can@02094000 {
|
|
compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x02094000 0x4000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
|
|
<&clks IMX6SX_CLK_CAN2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt: gpt@02098000 {
|
|
compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
|
|
reg = <0x02098000 0x4000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_GPT_BUS>,
|
|
<&clks IMX6SX_CLK_GPT_3M>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpio1: gpio@0209c000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x0209c000 0x4000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@020a0000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a0000 0x4000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@020a4000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a4000 0x4000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@020a8000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a8000 0x4000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio5: gpio@020ac000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020ac000 0x4000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio6: gpio@020b0000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b0000 0x4000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio7: gpio@020b4000 {
|
|
compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020b4000 0x4000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
kpp: kpp@020b8000 {
|
|
compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
|
|
reg = <0x020b8000 0x4000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog1: wdog@020bc000 {
|
|
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020bc000 0x4000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DUMMY>;
|
|
};
|
|
|
|
wdog2: wdog@020c0000 {
|
|
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020c0000 0x4000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clks: ccm@020c4000 {
|
|
compatible = "fsl,imx6sx-ccm";
|
|
reg = <0x020c4000 0x4000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <1>;
|
|
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
|
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
|
};
|
|
|
|
anatop: anatop@020c8000 {
|
|
compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
|
|
"syscon", "simple-bus";
|
|
reg = <0x020c8000 0x1000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
regulator-1p1@110 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd1p1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1375000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x110>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <4>;
|
|
anatop-min-voltage = <800000>;
|
|
anatop-max-voltage = <1375000>;
|
|
};
|
|
|
|
regulator-3p0@120 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd3p0";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <3150000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x120>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2625000>;
|
|
anatop-max-voltage = <3400000>;
|
|
};
|
|
|
|
regulator-2p5@130 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd2p5";
|
|
regulator-min-microvolt = <2100000>;
|
|
regulator-max-microvolt = <2875000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x130>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2100000>;
|
|
anatop-max-voltage = <2875000>;
|
|
};
|
|
|
|
reg_arm: regulator-vddcore@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddarm";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <0>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <24>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_pcie: regulator-vddpcie@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddpcie";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <9>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <26>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_soc: regulator-vddsoc@140 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddsoc";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <18>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <28>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
};
|
|
|
|
tempmon: tempmon {
|
|
compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
fsl,tempmon = <&anatop>;
|
|
fsl,tempmon-data = <&ocotp>;
|
|
clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
|
|
};
|
|
|
|
usbphy1: usbphy@020c9000 {
|
|
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020c9000 0x1000>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USBPHY1>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
usbphy2: usbphy@020ca000 {
|
|
compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020ca000 0x1000>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USBPHY2>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
snvs: snvs@020cc000 {
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
reg = <0x020cc000 0x4000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap = <&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
snvs_poweroff: snvs-poweroff {
|
|
compatible = "syscon-poweroff";
|
|
regmap = <&snvs>;
|
|
offset = <0x38>;
|
|
mask = <0x60>;
|
|
status = "disabled";
|
|
};
|
|
|
|
snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
epit1: epit@020d0000 {
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
epit2: epit@020d4000 {
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
src: src@020d8000 {
|
|
compatible = "fsl,imx6sx-src", "fsl,imx51-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@020dc000 {
|
|
compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
iomuxc: iomuxc@020e0000 {
|
|
compatible = "fsl,imx6sx-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@020e4000 {
|
|
compatible = "fsl,imx6sx-iomuxc-gpr",
|
|
"fsl,imx6q-iomuxc-gpr", "syscon";
|
|
reg = <0x020e4000 0x4000>;
|
|
};
|
|
|
|
sdma: sdma@020ec000 {
|
|
compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
|
|
reg = <0x020ec000 0x4000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_SDMA>,
|
|
<&clks IMX6SX_CLK_SDMA>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
/* imx6sx reuses imx6q sdma firmware */
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@02100000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
crypto: caam@2100000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
fsl,sec-era = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x2100000 0x10000>;
|
|
ranges = <0 0x2100000 0x10000>;
|
|
interrupt-parent = <&intc>;
|
|
clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
|
|
<&clks IMX6SX_CLK_CAAM_ACLK>,
|
|
<&clks IMX6SX_CLK_CAAM_IPG>,
|
|
<&clks IMX6SX_CLK_EIM_SLOW>;
|
|
clock-names = "mem", "aclk", "ipg", "emi_slow";
|
|
|
|
sec_jr0: jr0@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr1@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
usbotg1: usb@02184000 {
|
|
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
fsl,anatop = <&anatop>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg2: usb@02184200 {
|
|
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbh: usb@02184400 {
|
|
compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
|
|
reg = <0x02184400 0x200>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USBOH3>;
|
|
fsl,usbmisc = <&usbmisc 2>;
|
|
phy_type = "hsic";
|
|
fsl,anatop = <&anatop>;
|
|
dr_mode = "host";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@02184800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x02184800 0x200>;
|
|
clocks = <&clks IMX6SX_CLK_USBOH3>;
|
|
};
|
|
|
|
fec1: ethernet@02188000 {
|
|
compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_ENET>,
|
|
<&clks IMX6SX_CLK_ENET_AHB>,
|
|
<&clks IMX6SX_CLK_ENET_PTP>,
|
|
<&clks IMX6SX_CLK_ENET_REF>,
|
|
<&clks IMX6SX_CLK_ENET_PTP>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues=<3>;
|
|
fsl,num-rx-queues=<3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mlb: mlb@0218c000 {
|
|
reg = <0x0218c000 0x4000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_MLB>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@02190000 {
|
|
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USDHC1>,
|
|
<&clks IMX6SX_CLK_USDHC1>,
|
|
<&clks IMX6SX_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@02194000 {
|
|
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USDHC2>,
|
|
<&clks IMX6SX_CLK_USDHC2>,
|
|
<&clks IMX6SX_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc3: usdhc@02198000 {
|
|
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USDHC3>,
|
|
<&clks IMX6SX_CLK_USDHC3>,
|
|
<&clks IMX6SX_CLK_USDHC3>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc4: usdhc@0219c000 {
|
|
compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
|
|
reg = <0x0219c000 0x4000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_USDHC4>,
|
|
<&clks IMX6SX_CLK_USDHC4>,
|
|
<&clks IMX6SX_CLK_USDHC4>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@021a0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@021a4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@021a8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmdc: mmdc@021b0000 {
|
|
compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
};
|
|
|
|
fec2: ethernet@021b4000 {
|
|
compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
|
|
reg = <0x021b4000 0x4000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_ENET>,
|
|
<&clks IMX6SX_CLK_ENET_AHB>,
|
|
<&clks IMX6SX_CLK_ENET_PTP>,
|
|
<&clks IMX6SX_CLK_ENET2_REF_125M>,
|
|
<&clks IMX6SX_CLK_ENET_PTP>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
status = "disabled";
|
|
};
|
|
|
|
weim: weim@021b8000 {
|
|
compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
|
|
reg = <0x021b8000 0x4000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
|
|
};
|
|
|
|
ocotp: ocotp@021bc000 {
|
|
compatible = "fsl,imx6sx-ocotp", "syscon";
|
|
reg = <0x021bc000 0x4000>;
|
|
clocks = <&clks IMX6SX_CLK_OCOTP>;
|
|
};
|
|
|
|
sai1: sai@021d4000 {
|
|
compatible = "fsl,imx6sx-sai";
|
|
reg = <0x021d4000 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
|
|
<&clks IMX6SX_CLK_SAI1>,
|
|
<&clks 0>, <&clks 0>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "rx", "tx";
|
|
dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
|
|
dma-source = <&gpr 0 15 0 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
audmux: audmux@021d8000 {
|
|
compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
|
|
reg = <0x021d8000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@021dc000 {
|
|
compatible = "fsl,imx6sx-sai";
|
|
reg = <0x021dc000 0x4000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
|
|
<&clks IMX6SX_CLK_SAI2>,
|
|
<&clks 0>, <&clks 0>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dma-names = "rx", "tx";
|
|
dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
|
|
dma-source = <&gpr 0 17 0 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi1: qspi@021e0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-qspi";
|
|
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_QSPI1>,
|
|
<&clks IMX6SX_CLK_QSPI1>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi2: qspi@021e4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-qspi";
|
|
reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_QSPI2>,
|
|
<&clks IMX6SX_CLK_QSPI2>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@021e8000 {
|
|
compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
|
|
reg = <0x021e8000 0x4000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_UART_IPG>,
|
|
<&clks IMX6SX_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@021ec000 {
|
|
compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
|
|
reg = <0x021ec000 0x4000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_UART_IPG>,
|
|
<&clks IMX6SX_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@021f0000 {
|
|
compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
|
|
reg = <0x021f0000 0x4000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_UART_IPG>,
|
|
<&clks IMX6SX_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@021f4000 {
|
|
compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
|
|
reg = <0x021f4000 0x4000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_UART_IPG>,
|
|
<&clks IMX6SX_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@021f8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021f8000 0x4000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_I2C4>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips3: aips-bus@02200000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02200000 0x100000>;
|
|
ranges;
|
|
|
|
spba-bus@02200000 {
|
|
compatible = "fsl,spba-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02240000 0x40000>;
|
|
ranges;
|
|
|
|
csi1: csi@02214000 {
|
|
reg = <0x02214000 0x4000>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
|
|
<&clks IMX6SX_CLK_CSI>,
|
|
<&clks IMX6SX_CLK_DCIC1>;
|
|
clock-names = "disp-axi", "csi_mclk", "dcic";
|
|
status = "disabled";
|
|
};
|
|
|
|
pxp: pxp@02218000 {
|
|
reg = <0x02218000 0x4000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PXP_AXI>,
|
|
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
|
clock-names = "pxp-axi", "disp-axi";
|
|
status = "disabled";
|
|
};
|
|
|
|
csi2: csi@0221c000 {
|
|
reg = <0x0221c000 0x4000>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
|
|
<&clks IMX6SX_CLK_CSI>,
|
|
<&clks IMX6SX_CLK_DCIC2>;
|
|
clock-names = "disp-axi", "csi_mclk", "dcic";
|
|
status = "disabled";
|
|
};
|
|
|
|
lcdif1: lcdif@02220000 {
|
|
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
|
|
reg = <0x02220000 0x4000>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
|
|
<&clks IMX6SX_CLK_LCDIF_APB>,
|
|
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
|
clock-names = "pix", "axi", "disp_axi";
|
|
status = "disabled";
|
|
};
|
|
|
|
lcdif2: lcdif@02224000 {
|
|
compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
|
|
reg = <0x02224000 0x4000>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
|
|
<&clks IMX6SX_CLK_LCDIF_APB>,
|
|
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
|
clock-names = "pix", "axi", "disp_axi";
|
|
status = "disabled";
|
|
};
|
|
|
|
vadc: vadc@02228000 {
|
|
reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
|
|
reg-names = "vadc-vafe", "vadc-vdec";
|
|
clocks = <&clks IMX6SX_CLK_VADC>,
|
|
<&clks IMX6SX_CLK_CSI>;
|
|
clock-names = "vadc", "csi";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
adc1: adc@02280000 {
|
|
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
|
|
reg = <0x02280000 0x4000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_IPG>;
|
|
clock-names = "adc";
|
|
status = "disabled";
|
|
};
|
|
|
|
adc2: adc@02284000 {
|
|
compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
|
|
reg = <0x02284000 0x4000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_IPG>;
|
|
clock-names = "adc";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: wdog@02288000 {
|
|
compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
|
|
reg = <0x02288000 0x4000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_DUMMY>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ecspi5: ecspi@0228c000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
|
|
reg = <0x0228c000 0x4000>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_ECSPI5>,
|
|
<&clks IMX6SX_CLK_ECSPI5>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@022a0000 {
|
|
compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
|
|
reg = <0x022a0000 0x4000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_UART_IPG>,
|
|
<&clks IMX6SX_CLK_UART_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@022a4000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x022a4000 0x4000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM5>,
|
|
<&clks IMX6SX_CLK_PWM5>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pwm6: pwm@022a8000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x022a8000 0x4000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM6>,
|
|
<&clks IMX6SX_CLK_PWM6>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pwm7: pwm@022ac000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x022ac000 0x4000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM7>,
|
|
<&clks IMX6SX_CLK_PWM7>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pwm8: pwm@0022b0000 {
|
|
compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
|
|
reg = <0x0022b0000 0x4000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PWM8>,
|
|
<&clks IMX6SX_CLK_PWM8>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
};
|
|
};
|
|
|
|
pcie: pcie@0x08000000 {
|
|
compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
|
|
reg = <0x08ffc000 0x4000>; /* DBI */
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
/* configuration space */
|
|
ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
|
|
/* downstream I/O */
|
|
0x81000000 0 0 0x08f80000 0 0x00010000
|
|
/* non-prefetchable memory */
|
|
0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
|
|
num-lanes = <1>;
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
|
|
<&clks IMX6SX_CLK_PCIE_AXI>,
|
|
<&clks IMX6SX_CLK_LVDS1_OUT>,
|
|
<&clks IMX6SX_CLK_DISPLAY_AXI>;
|
|
clock-names = "pcie_ref_125m", "pcie_axi",
|
|
"lvds_gate", "display_axi";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|