055223d4d2
This enables the available eTSEC ethernet ports for the ls1021aqds and ls1021atwr boards. For the QDS, SGMII connections (via riser cards) are assumed for the eTSEC0 and eTSEC1 ports as default configuration. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
330 lines
7 KiB
Plaintext
330 lines
7 KiB
Plaintext
/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "ls1021a.dtsi"
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/ {
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model = "LS1021A QDS Board";
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aliases {
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enet0_rgmii_phy = &rgmii_phy1;
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enet1_rgmii_phy = &rgmii_phy2;
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enet2_rgmii_phy = &rgmii_phy3;
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enet0_sgmii_phy = &sgmii_phy1c;
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enet1_sgmii_phy = &sgmii_phy1d;
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};
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sys_mclk: clock-mclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3p3v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Speaker", "Speaker Ext",
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"Line", "Line In Jack";
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simple-audio-card,routing =
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"MIC_IN", "Microphone Jack",
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"Microphone Jack", "Mic Bias",
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"LINE_IN", "Line In Jack",
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"Headphone Jack", "HP_OUT",
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"Speaker Ext", "LINE_OUT";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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frame-master;
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bitclock-master;
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};
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simple-audio-card,codec {
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sound-dai = <&codec>;
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frame-master;
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bitclock-master;
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};
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dspiflash: at45db021d@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
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spi-max-frequency = <16000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&enet0 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy1c>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet1 {
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tbi-handle = <&tbi0>;
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phy-handle = <&sgmii_phy1d>;
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phy-connection-type = "sgmii";
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status = "okay";
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};
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&enet2 {
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phy-handle = <&rgmii_phy3>;
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phy-connection-type = "rgmii-id";
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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pca9547: mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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ds3232: rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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eeprom@56 {
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compatible = "atmel,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c512";
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reg = <0x57>;
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};
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adt7461a@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4>;
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codec: sgtl5000@2a {
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#sound-dai-cells = <0>;
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compatible = "fsl,sgtl5000";
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reg = <0x2a>;
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VDDA-supply = <®_3p3v>;
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VDDIO-supply = <®_3p3v>;
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clocks = <&sys_mclk 1>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NOR, NAND Flashes and FPGA on board */
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ranges = <0x0 0x0 0x0 0x60000000 0x08000000
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0x2 0x0 0x0 0x7e800000 0x00010000
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0x3 0x0 0x0 0x7fb00000 0x00000100>;
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status = "okay";
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x3 0x0 0x0000100>;
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bank-width = <1>;
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device-width = <1>;
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ranges = <0 3 0 0x100>;
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mdio-mux-emi1 {
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compatible = "mdio-mux-mmioreg";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x54 1>; /* BRDCFG4 */
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mux-mask = <0xe0>; /* EMI1[2:0] */
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/* Onboard PHYs */
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ls1021amdio0: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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ls1021amdio1: mdio@20 {
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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ls1021amdio2: mdio@40 {
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgmii_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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ls1021amdio3: mdio@60 {
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1c: ethernet-phy@1c {
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reg = <0x1c>;
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};
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};
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ls1021amdio4: mdio@80 {
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reg = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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sgmii_phy1d: ethernet-phy@1d {
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reg = <0x1d>;
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};
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};
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};
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};
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};
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&lpuart0 {
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status = "okay";
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};
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&mdio0 {
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tbi0: tbi-phy@8 {
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reg = <0x8>;
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device_type = "tbi-phy";
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};
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};
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&sai2 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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