![Carlo Caione](/assets/img/avatar_default.png)
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
188 lines
4.5 KiB
C
188 lines
4.5 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __CLKC_H
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#define __CLKC_H
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#define PMASK(width) GENMASK(width - 1, 0)
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#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
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#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
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#define PARM_GET(width, shift, reg) \
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(((reg) & SETPMASK(width, shift)) >> (shift))
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#define PARM_SET(width, shift, reg, val) \
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(((reg) & CLRPMASK(width, shift)) | (val << (shift)))
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#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
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struct parm {
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u16 reg_off;
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u8 shift;
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u8 width;
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};
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#define PARM(_r, _s, _w) \
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{ \
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.reg_off = (_r), \
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.shift = (_s), \
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.width = (_w), \
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} \
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struct pll_rate_table {
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unsigned long rate;
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u16 m;
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u16 n;
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u16 od;
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};
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#define PLL_RATE(_r, _m, _n, _od) \
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{ \
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.rate = (_r), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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} \
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struct pll_conf {
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const struct pll_rate_table *rate_table;
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struct parm m;
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struct parm n;
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struct parm od;
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};
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struct fixed_fact_conf {
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unsigned int div;
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unsigned int mult;
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struct parm div_parm;
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struct parm mult_parm;
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};
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struct fixed_rate_conf {
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unsigned long rate;
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struct parm rate_parm;
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};
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struct composite_conf {
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struct parm mux_parm;
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struct parm div_parm;
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struct parm gate_parm;
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struct clk_div_table *div_table;
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u32 *mux_table;
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u8 mux_flags;
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u8 div_flags;
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u8 gate_flags;
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};
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#define PNAME(x) static const char *x[]
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enum clk_type {
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CLK_FIXED_FACTOR,
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CLK_FIXED_RATE,
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CLK_COMPOSITE,
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CLK_CPU,
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CLK_PLL,
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};
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struct clk_conf {
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u16 reg_off;
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enum clk_type clk_type;
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unsigned int clk_id;
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const char *clk_name;
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const char **clks_parent;
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int num_parents;
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unsigned long flags;
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union {
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struct fixed_fact_conf fixed_fact;
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struct fixed_rate_conf fixed_rate;
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const struct composite_conf *composite;
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struct pll_conf *pll;
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const struct clk_div_table *div_table;
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} conf;
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};
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#define FIXED_RATE_P(_ro, _ci, _cn, _f, _c) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_FIXED_RATE, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.flags = (_f), \
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.conf.fixed_rate.rate_parm = _c, \
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} \
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#define FIXED_RATE(_ci, _cn, _f, _r) \
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{ \
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.clk_type = CLK_FIXED_RATE, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.flags = (_f), \
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.conf.fixed_rate.rate = (_r), \
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} \
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#define PLL(_ro, _ci, _cn, _cp, _f, _c) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_PLL, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.clks_parent = (_cp), \
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.num_parents = ARRAY_SIZE(_cp), \
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.flags = (_f), \
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.conf.pll = (_c), \
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} \
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#define FIXED_FACTOR_DIV(_ci, _cn, _cp, _f, _d) \
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{ \
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.clk_type = CLK_FIXED_FACTOR, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.clks_parent = (_cp), \
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.num_parents = ARRAY_SIZE(_cp), \
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.conf.fixed_fact.div = (_d), \
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} \
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#define CPU(_ro, _ci, _cn, _cp, _dt) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_CPU, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.clks_parent = (_cp), \
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.num_parents = ARRAY_SIZE(_cp), \
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.conf.div_table = (_dt), \
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} \
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#define COMPOSITE(_ro, _ci, _cn, _cp, _f, _c) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_COMPOSITE, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.clks_parent = (_cp), \
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.num_parents = ARRAY_SIZE(_cp), \
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.flags = (_f), \
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.conf.composite = (_c), \
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} \
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struct clk **meson_clk_init(struct device_node *np, unsigned long nr_clks);
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void meson_clk_register_clks(const struct clk_conf *clk_confs,
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unsigned int nr_confs, void __iomem *clk_base);
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struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
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void __iomem *reg_base, spinlock_t *lock);
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struct clk *meson_clk_register_pll(const struct clk_conf *clk_conf,
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void __iomem *reg_base, spinlock_t *lock);
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#endif /* __CLKC_H */
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