![Linus Torvalds](/assets/img/avatar_default.png)
Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - Memory controller work for ARM's PL172 memory controller - Reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5Ou9AAoJEIwa5zzehBx3/k4P/jA5CVNiDvIs0GoTR3uGOuec MYd19oKf76reV1oL5bBSpg9uryJd3fPzK0JC/qU3pYfsCVFp2TWZD7liNpitqHyt 2xL02gzJQgjHzL3QrxTQrOFJDO6P8Vm2k/5pI0KX1beoulHvI+iHejNryXGjSKSx 9vbs1GPXU9IV831YOHSaMmHz727J65bbZE8Up113ctT+WbEIc1g/ihKzUgi/8xXW RniMxGsX8HynE3VH+UBDMbY6XkOmzZa1Wabgll735MXwIUFG1+TsvHNuGehXUski ySwqk67en25i0F/Q7oobLSZwCPbA6Ylxk9aOfr0AnAqOEKwgKWS+K7HkEiNMz7yh nt22b5SVkQ80sTCbNEkdJajOZ8oRalUae19CGxvMfVh77LmQ2sRI9iJrwXcxkt8W ASs6uDDAUNC5pIWfjeJE50vsDr//Hed/WtsIjenYOtb+RI1kru5iTTgp4oLPBiy5 OeHxOfiL7gPvyZQbuPgMKAGdoGBsa/7wTM7KWJCMP6mPGHpShO8XUUsuljqKHm4w nBV7eZRMiIuWkjRKw4bjp7R0NVKR5sOfAkZhjCsXB0aqA/NU2zyNbViWcGCh6yj8 3beZ93SdEdrKX6N8pPiAhGTMFA6eev8YeUHO7kM4IhC91ILjHlPpCs1pYk3pwEkO ABC7GyMY6Olg1pZJweEa =B6jn -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/*
|
|
* r8a7778 Core CPG Clocks
|
|
*
|
|
* Copyright (C) 2014 Ulrich Hecht
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/clk/shmobile.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/slab.h>
|
|
|
|
struct r8a7778_cpg {
|
|
struct clk_onecell_data data;
|
|
spinlock_t lock;
|
|
void __iomem *reg;
|
|
};
|
|
|
|
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
|
|
struct {
|
|
unsigned long plla_mult;
|
|
unsigned long pllb_mult;
|
|
} r8a7778_rates[] __initdata = {
|
|
[0] = { 21, 21 },
|
|
[1] = { 24, 24 },
|
|
[2] = { 28, 28 },
|
|
[3] = { 32, 32 },
|
|
[5] = { 24, 21 },
|
|
[6] = { 28, 21 },
|
|
[7] = { 32, 24 },
|
|
};
|
|
|
|
/* Clock dividers per bits 1 and 2 of MODEMR */
|
|
struct {
|
|
const char *name;
|
|
unsigned int div[4];
|
|
} r8a7778_divs[6] __initdata = {
|
|
{ "b", { 12, 12, 16, 18 } },
|
|
{ "out", { 12, 12, 16, 18 } },
|
|
{ "p", { 16, 12, 16, 12 } },
|
|
{ "s", { 4, 3, 4, 3 } },
|
|
{ "s1", { 8, 6, 8, 6 } },
|
|
};
|
|
|
|
static u32 cpg_mode_rates __initdata;
|
|
static u32 cpg_mode_divs __initdata;
|
|
|
|
static struct clk * __init
|
|
r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
|
|
const char *name)
|
|
{
|
|
if (!strcmp(name, "plla")) {
|
|
return clk_register_fixed_factor(NULL, "plla",
|
|
of_clk_get_parent_name(np, 0), 0,
|
|
r8a7778_rates[cpg_mode_rates].plla_mult, 1);
|
|
} else if (!strcmp(name, "pllb")) {
|
|
return clk_register_fixed_factor(NULL, "pllb",
|
|
of_clk_get_parent_name(np, 0), 0,
|
|
r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
|
|
} else {
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
|
|
if (!strcmp(name, r8a7778_divs[i].name)) {
|
|
return clk_register_fixed_factor(NULL,
|
|
r8a7778_divs[i].name,
|
|
"plla", 0, 1,
|
|
r8a7778_divs[i].div[cpg_mode_divs]);
|
|
}
|
|
}
|
|
}
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
|
|
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
|
|
{
|
|
struct r8a7778_cpg *cpg;
|
|
struct clk **clks;
|
|
unsigned int i;
|
|
int num_clks;
|
|
|
|
num_clks = of_property_count_strings(np, "clock-output-names");
|
|
if (num_clks < 0) {
|
|
pr_err("%s: failed to count clocks\n", __func__);
|
|
return;
|
|
}
|
|
|
|
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
|
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
|
if (cpg == NULL || clks == NULL) {
|
|
/* We're leaking memory on purpose, there's no point in cleaning
|
|
* up as the system won't boot anyway.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
spin_lock_init(&cpg->lock);
|
|
|
|
cpg->data.clks = clks;
|
|
cpg->data.clk_num = num_clks;
|
|
|
|
cpg->reg = of_iomap(np, 0);
|
|
if (WARN_ON(cpg->reg == NULL))
|
|
return;
|
|
|
|
for (i = 0; i < num_clks; ++i) {
|
|
const char *name;
|
|
struct clk *clk;
|
|
|
|
of_property_read_string_index(np, "clock-output-names", i,
|
|
&name);
|
|
|
|
clk = r8a7778_cpg_register_clock(np, cpg, name);
|
|
if (IS_ERR(clk))
|
|
pr_err("%s: failed to register %s %s clock (%ld)\n",
|
|
__func__, np->name, name, PTR_ERR(clk));
|
|
else
|
|
cpg->data.clks[i] = clk;
|
|
}
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
|
|
|
cpg_mstp_add_clk_domain(np);
|
|
}
|
|
|
|
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
|
|
r8a7778_cpg_clocks_init);
|
|
|
|
void __init r8a7778_clocks_init(u32 mode)
|
|
{
|
|
BUG_ON(!(mode & BIT(19)));
|
|
|
|
cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
|
|
(!!(mode & BIT(12)) << 1) |
|
|
(!!(mode & BIT(11)));
|
|
cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
|
|
(!!(mode & BIT(1)));
|
|
|
|
of_clk_init(NULL);
|
|
}
|