![Linus Torvalds](/assets/img/avatar_default.png)
Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - Memory controller work for ARM's PL172 memory controller - Reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5Ou9AAoJEIwa5zzehBx3/k4P/jA5CVNiDvIs0GoTR3uGOuec MYd19oKf76reV1oL5bBSpg9uryJd3fPzK0JC/qU3pYfsCVFp2TWZD7liNpitqHyt 2xL02gzJQgjHzL3QrxTQrOFJDO6P8Vm2k/5pI0KX1beoulHvI+iHejNryXGjSKSx 9vbs1GPXU9IV831YOHSaMmHz727J65bbZE8Up113ctT+WbEIc1g/ihKzUgi/8xXW RniMxGsX8HynE3VH+UBDMbY6XkOmzZa1Wabgll735MXwIUFG1+TsvHNuGehXUski ySwqk67en25i0F/Q7oobLSZwCPbA6Ylxk9aOfr0AnAqOEKwgKWS+K7HkEiNMz7yh nt22b5SVkQ80sTCbNEkdJajOZ8oRalUae19CGxvMfVh77LmQ2sRI9iJrwXcxkt8W ASs6uDDAUNC5pIWfjeJE50vsDr//Hed/WtsIjenYOtb+RI1kru5iTTgp4oLPBiy5 OeHxOfiL7gPvyZQbuPgMKAGdoGBsa/7wTM7KWJCMP6mPGHpShO8XUUsuljqKHm4w nBV7eZRMiIuWkjRKw4bjp7R0NVKR5sOfAkZhjCsXB0aqA/NU2zyNbViWcGCh6yj8 3beZ93SdEdrKX6N8pPiAhGTMFA6eev8YeUHO7kM4IhC91ILjHlPpCs1pYk3pwEkO ABC7GyMY6Olg1pZJweEa =B6jn -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
430 lines
11 KiB
C
430 lines
11 KiB
C
/*
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* rcar_gen2 Core CPG Clocks
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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*
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* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/shmobile.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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struct rcar_gen2_cpg {
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struct clk_onecell_data data;
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spinlock_t lock;
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void __iomem *reg;
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};
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#define CPG_FRQCRB 0x00000004
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_SDCKCR 0x00000074
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#define CPG_PLL0CR 0x000000d8
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#define CPG_FRQCRC 0x000000e0
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#define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
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#define CPG_FRQCRC_ZFC_SHIFT 8
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#define CPG_ADSPCKCR 0x0000025c
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#define CPG_RCANCKCR 0x00000270
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/* -----------------------------------------------------------------------------
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* Z Clock
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate * mult / 32
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* parent - fixed parent. No clk_set_parent support
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*/
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struct cpg_z_clk {
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *kick_reg;
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};
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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unsigned int val;
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val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
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>> CPG_FRQCRC_ZFC_SHIFT;
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mult = 32 - val;
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return div_u64((u64)parent_rate * mult, 32);
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}
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static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long prate = *parent_rate;
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unsigned int mult;
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if (!prate)
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prate = 1;
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mult = div_u64((u64)rate * 32, prate);
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mult = clamp(mult, 1U, 32U);
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return *parent_rate / 32 * mult;
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}
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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u32 val, kick;
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unsigned int i;
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mult = div_u64((u64)rate * 32, parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = clk_readl(zclk->reg);
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val &= ~CPG_FRQCRC_ZFC_MASK;
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val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
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clk_writel(val, zclk->reg);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = clk_readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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clk_writel(kick, zclk->kick_reg);
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/*
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* Note: There is no HW information about the worst case latency.
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*
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* Using experimental measurements, it seems that no more than
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* ~10 iterations are needed, independently of the CPU rate.
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* Since this value might be dependant of external xtal rate, pll1
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* rate or even the other emulation clocks rate, use 1000 as a
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static const struct clk_ops cpg_z_clk_ops = {
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.recalc_rate = cpg_z_clk_recalc_rate,
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.round_rate = cpg_z_clk_round_rate,
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.set_rate = cpg_z_clk_set_rate,
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};
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static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
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{
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static const char *parent_name = "pll0";
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struct clk_init_data init;
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struct cpg_z_clk *zclk;
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struct clk *clk;
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
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if (!zclk)
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return ERR_PTR(-ENOMEM);
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init.name = "z";
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init.ops = &cpg_z_clk_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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zclk->reg = cpg->reg + CPG_FRQCRC;
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zclk->kick_reg = cpg->reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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clk = clk_register(NULL, &zclk->hw);
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if (IS_ERR(clk))
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kfree(zclk);
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return clk;
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}
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static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
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struct device_node *np)
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{
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const char *parent_name = of_clk_get_parent_name(np, 1);
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struct clk_fixed_factor *fixed;
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struct clk_gate *gate;
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struct clk *clk;
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fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
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if (!fixed)
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return ERR_PTR(-ENOMEM);
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fixed->mult = 1;
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fixed->div = 6;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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kfree(fixed);
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return ERR_PTR(-ENOMEM);
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}
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gate->reg = cpg->reg + CPG_RCANCKCR;
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gate->bit_idx = 8;
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gate->flags = CLK_GATE_SET_TO_DISABLE;
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gate->lock = &cpg->lock;
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clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
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&fixed->hw, &clk_fixed_factor_ops,
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&gate->hw, &clk_gate_ops, 0);
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if (IS_ERR(clk)) {
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kfree(gate);
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kfree(fixed);
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}
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return clk;
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}
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/* ADSP divisors */
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static const struct clk_div_table cpg_adsp_div_table[] = {
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{ 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
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{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
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{ 10, 36 }, { 11, 48 }, { 0, 0 },
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};
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static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
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{
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const char *parent_name = "pll1";
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struct clk_divider *div;
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struct clk_gate *gate;
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struct clk *clk;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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div->reg = cpg->reg + CPG_ADSPCKCR;
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div->width = 4;
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div->table = cpg_adsp_div_table;
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div->lock = &cpg->lock;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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kfree(div);
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return ERR_PTR(-ENOMEM);
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}
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gate->reg = cpg->reg + CPG_ADSPCKCR;
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gate->bit_idx = 8;
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gate->flags = CLK_GATE_SET_TO_DISABLE;
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gate->lock = &cpg->lock;
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clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
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&div->hw, &clk_divider_ops,
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&gate->hw, &clk_gate_ops, 0);
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if (IS_ERR(clk)) {
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kfree(gate);
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kfree(div);
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}
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return clk;
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}
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/* -----------------------------------------------------------------------------
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *1
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*---------------------------------------------------
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* 0 0 0 15 x 1 x172/2 x208/2 x106
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* 0 0 1 15 x 1 x172/2 x208/2 x88
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* 0 1 0 20 x 1 x130/2 x156/2 x80
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* 0 1 1 20 x 1 x130/2 x156/2 x66
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* 1 0 0 26 / 2 x200/2 x240/2 x122
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* 1 0 1 26 / 2 x200/2 x240/2 x102
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* 1 1 0 30 / 2 x172/2 x208/2 x106
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* 1 1 1 30 / 2 x172/2 x208/2 x88
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*
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* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
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(((md) & BIT(13)) >> 12) | \
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(((md) & BIT(19)) >> 19))
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struct cpg_pll_config {
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unsigned int extal_div;
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unsigned int pll1_mult;
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unsigned int pll3_mult;
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};
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static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
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{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
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{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
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};
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/* SDHI divisors */
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static const struct clk_div_table cpg_sdh_div_table[] = {
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
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};
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static const struct clk_div_table cpg_sd01_div_table[] = {
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{ 4, 8 },
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{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
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{ 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
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};
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static u32 cpg_mode __initdata;
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static struct clk * __init
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rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
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const struct cpg_pll_config *config,
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const char *name)
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{
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const struct clk_div_table *table = NULL;
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const char *parent_name;
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unsigned int shift;
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unsigned int mult = 1;
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unsigned int div = 1;
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if (!strcmp(name, "main")) {
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parent_name = of_clk_get_parent_name(np, 0);
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div = config->extal_div;
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} else if (!strcmp(name, "pll0")) {
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/* PLL0 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
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parent_name = "main";
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mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
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} else if (!strcmp(name, "pll1")) {
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parent_name = "main";
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mult = config->pll1_mult / 2;
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} else if (!strcmp(name, "pll3")) {
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parent_name = "main";
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mult = config->pll3_mult;
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} else if (!strcmp(name, "lb")) {
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parent_name = "pll1";
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div = cpg_mode & BIT(18) ? 36 : 24;
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} else if (!strcmp(name, "qspi")) {
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parent_name = "pll1_div2";
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div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
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? 8 : 10;
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} else if (!strcmp(name, "sdh")) {
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parent_name = "pll1";
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table = cpg_sdh_div_table;
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shift = 8;
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} else if (!strcmp(name, "sd0")) {
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parent_name = "pll1";
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table = cpg_sd01_div_table;
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shift = 4;
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} else if (!strcmp(name, "sd1")) {
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parent_name = "pll1";
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table = cpg_sd01_div_table;
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shift = 0;
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} else if (!strcmp(name, "z")) {
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return cpg_z_clk_register(cpg);
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} else if (!strcmp(name, "rcan")) {
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return cpg_rcan_clk_register(cpg, np);
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} else if (!strcmp(name, "adsp")) {
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return cpg_adsp_clk_register(cpg);
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} else {
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return ERR_PTR(-EINVAL);
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}
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if (!table)
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return clk_register_fixed_factor(NULL, name, parent_name, 0,
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mult, div);
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else
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return clk_register_divider_table(NULL, name, parent_name, 0,
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cpg->reg + CPG_SDCKCR, shift,
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4, 0, table, &cpg->lock);
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}
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static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
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{
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const struct cpg_pll_config *config;
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struct rcar_gen2_cpg *cpg;
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struct clk **clks;
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unsigned int i;
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int num_clks;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (num_clks < 0) {
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pr_err("%s: failed to count clocks\n", __func__);
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return;
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}
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
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if (cpg == NULL || clks == NULL) {
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/* We're leaking memory on purpose, there's no point in cleaning
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* up as the system won't boot anyway.
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*/
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pr_err("%s: failed to allocate cpg\n", __func__);
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return;
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}
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spin_lock_init(&cpg->lock);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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if (WARN_ON(cpg->reg == NULL))
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return;
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config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i,
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&name);
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clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clk));
|
|
else
|
|
cpg->data.clks[i] = clk;
|
|
}
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
|
|
|
cpg_mstp_add_clk_domain(np);
|
|
}
|
|
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
|
|
rcar_gen2_cpg_clocks_init);
|
|
|
|
void __init rcar_gen2_clocks_init(u32 mode)
|
|
{
|
|
cpg_mode = mode;
|
|
|
|
of_clk_init(NULL);
|
|
}
|