![Stephen Boyd](/assets/img/avatar_default.png)
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. Also add in a clkdev.h include that was missing in a file using clkdev APIs. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
171 lines
4.6 KiB
C
171 lines
4.6 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <soc/tegra/fuse.h>
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#include "clk.h"
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static DEFINE_SPINLOCK(periph_ref_lock);
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/* Macros to assist peripheral gate clock */
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#define read_enb(gate) \
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readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
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#define write_enb_set(val, gate) \
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writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
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#define write_enb_clr(val, gate) \
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writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
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#define read_rst(gate) \
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readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
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#define write_rst_clr(val, gate) \
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writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
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#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
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#define LVL2_CLK_GATE_OVRE 0x554
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/* Peripheral gate clock ops */
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static int clk_periph_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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int state = 1;
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if (!(read_enb(gate) & periph_clk_to_bit(gate)))
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state = 0;
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if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
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if (read_rst(gate) & periph_clk_to_bit(gate))
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state = 0;
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return state;
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}
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static int clk_periph_enable(struct clk_hw *hw)
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{
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struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(&periph_ref_lock, flags);
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gate->enable_refcnt[gate->clk_num]++;
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if (gate->enable_refcnt[gate->clk_num] > 1) {
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spin_unlock_irqrestore(&periph_ref_lock, flags);
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return 0;
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}
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write_enb_set(periph_clk_to_bit(gate), gate);
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udelay(2);
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if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
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!(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
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if (read_rst(gate) & periph_clk_to_bit(gate)) {
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udelay(5); /* reset propogation delay */
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write_rst_clr(periph_clk_to_bit(gate), gate);
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}
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}
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if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
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writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
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udelay(1);
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writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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}
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spin_unlock_irqrestore(&periph_ref_lock, flags);
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return 0;
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}
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static void clk_periph_disable(struct clk_hw *hw)
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{
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struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(&periph_ref_lock, flags);
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gate->enable_refcnt[gate->clk_num]--;
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if (gate->enable_refcnt[gate->clk_num] > 0) {
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spin_unlock_irqrestore(&periph_ref_lock, flags);
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return;
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}
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/*
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* If peripheral is in the APB bus then read the APB bus to
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* flush the write operation in apb bus. This will avoid the
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* peripheral access after disabling clock
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*/
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if (gate->flags & TEGRA_PERIPH_ON_APB)
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tegra_read_chipid();
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write_enb_clr(periph_clk_to_bit(gate), gate);
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spin_unlock_irqrestore(&periph_ref_lock, flags);
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}
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const struct clk_ops tegra_clk_periph_gate_ops = {
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.is_enabled = clk_periph_is_enabled,
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.enable = clk_periph_enable,
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.disable = clk_periph_disable,
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};
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struct clk *tegra_clk_register_periph_gate(const char *name,
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const char *parent_name, u8 gate_flags, void __iomem *clk_base,
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unsigned long flags, int clk_num, int *enable_refcnt)
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{
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struct tegra_clk_periph_gate *gate;
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struct clk *clk;
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struct clk_init_data init;
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struct tegra_clk_periph_regs *pregs;
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pregs = get_reg_bank(clk_num);
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if (!pregs)
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return ERR_PTR(-EINVAL);
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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pr_err("%s: could not allocate periph gate clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.ops = &tegra_clk_periph_gate_ops;
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gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
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gate->clk_base = clk_base;
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gate->clk_num = clk_num;
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gate->flags = gate_flags;
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gate->enable_refcnt = enable_refcnt;
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gate->regs = pregs;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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gate->hw.init = &init;
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clk = clk_register(NULL, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}
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