![Stephen Boyd](/assets/img/avatar_default.png)
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
665 lines
15 KiB
C
665 lines
15 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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/* FAPLL Control Register PLL_CTRL */
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#define FAPLL_MAIN_MULT_N_SHIFT 16
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#define FAPLL_MAIN_DIV_P_SHIFT 8
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#define FAPLL_MAIN_LOCK BIT(7)
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#define FAPLL_MAIN_PLLEN BIT(3)
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#define FAPLL_MAIN_BP BIT(2)
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#define FAPLL_MAIN_LOC_CTL BIT(0)
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#define FAPLL_MAIN_MAX_MULT_N 0xffff
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#define FAPLL_MAIN_MAX_DIV_P 0xff
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#define FAPLL_MAIN_CLEAR_MASK \
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((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
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(FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
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FAPLL_MAIN_LOC_CTL)
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/* FAPLL powerdown register PWD */
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#define FAPLL_PWD_OFFSET 4
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#define MAX_FAPLL_OUTPUTS 7
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#define FAPLL_MAX_RETRIES 1000
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#define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
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#define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
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/* The bypass bit is inverted on the ddr_pll.. */
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#define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
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/*
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* The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
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* and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
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*/
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#define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
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#define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
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/* Synthesizer divider register */
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#define SYNTH_LDMDIV1 BIT(8)
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/* Synthesizer frequency register */
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#define SYNTH_LDFREQ BIT(31)
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#define SYNTH_PHASE_K 8
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#define SYNTH_MAX_INT_DIV 0xf
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#define SYNTH_MAX_DIV_M 0xff
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struct fapll_data {
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struct clk_hw hw;
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void __iomem *base;
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const char *name;
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struct clk *clk_ref;
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struct clk *clk_bypass;
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struct clk_onecell_data outputs;
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bool bypass_bit_inverted;
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};
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struct fapll_synth {
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struct clk_hw hw;
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struct fapll_data *fd;
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int index;
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void __iomem *freq;
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void __iomem *div;
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const char *name;
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struct clk *clk_pll;
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};
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static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
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{
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u32 v = readl_relaxed(fd->base);
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if (fd->bypass_bit_inverted)
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return !(v & FAPLL_MAIN_BP);
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else
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return !!(v & FAPLL_MAIN_BP);
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}
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static void ti_fapll_set_bypass(struct fapll_data *fd)
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{
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u32 v = readl_relaxed(fd->base);
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if (fd->bypass_bit_inverted)
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v &= ~FAPLL_MAIN_BP;
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else
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v |= FAPLL_MAIN_BP;
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writel_relaxed(v, fd->base);
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}
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static void ti_fapll_clear_bypass(struct fapll_data *fd)
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{
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u32 v = readl_relaxed(fd->base);
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if (fd->bypass_bit_inverted)
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v |= FAPLL_MAIN_BP;
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else
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v &= ~FAPLL_MAIN_BP;
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writel_relaxed(v, fd->base);
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}
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static int ti_fapll_wait_lock(struct fapll_data *fd)
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{
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int retries = FAPLL_MAX_RETRIES;
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u32 v;
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while ((v = readl_relaxed(fd->base))) {
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if (v & FAPLL_MAIN_LOCK)
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return 0;
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if (retries-- <= 0)
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break;
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udelay(1);
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}
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pr_err("%s failed to lock\n", fd->name);
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return -ETIMEDOUT;
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}
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static int ti_fapll_enable(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v |= FAPLL_MAIN_PLLEN;
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writel_relaxed(v, fd->base);
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ti_fapll_wait_lock(fd);
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return 0;
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}
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static void ti_fapll_disable(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v &= ~FAPLL_MAIN_PLLEN;
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writel_relaxed(v, fd->base);
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}
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static int ti_fapll_is_enabled(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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return v & FAPLL_MAIN_PLLEN;
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}
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static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 fapll_n, fapll_p, v;
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long long rate;
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if (ti_fapll_clock_is_bypass(fd))
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return parent_rate;
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rate = parent_rate;
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/* PLL pre-divider is P and multiplier is N */
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v = readl_relaxed(fd->base);
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fapll_p = (v >> 8) & 0xff;
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if (fapll_p)
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do_div(rate, fapll_p);
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fapll_n = v >> 16;
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if (fapll_n)
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rate *= fapll_n;
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return rate;
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}
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static u8 ti_fapll_get_parent(struct clk_hw *hw)
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{
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struct fapll_data *fd = to_fapll(hw);
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if (ti_fapll_clock_is_bypass(fd))
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return 1;
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return 0;
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}
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static int ti_fapll_set_div_mult(unsigned long rate,
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unsigned long parent_rate,
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u32 *pre_div_p, u32 *mult_n)
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{
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/*
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* So far no luck getting decent clock with PLL divider,
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* PLL does not seem to lock and the signal does not look
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* right. It seems the divider can only be used together
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* with the multiplier?
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*/
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if (rate < parent_rate) {
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pr_warn("FAPLL main divider rates unsupported\n");
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return -EINVAL;
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}
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*mult_n = rate / parent_rate;
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if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
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return -EINVAL;
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*pre_div_p = 1;
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return 0;
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}
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static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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u32 pre_div_p, mult_n;
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int error;
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if (!rate)
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return -EINVAL;
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error = ti_fapll_set_div_mult(rate, *parent_rate,
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&pre_div_p, &mult_n);
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if (error)
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return error;
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rate = *parent_rate / pre_div_p;
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rate *= mult_n;
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return rate;
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}
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static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct fapll_data *fd = to_fapll(hw);
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u32 pre_div_p, mult_n, v;
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int error;
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if (!rate)
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return -EINVAL;
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error = ti_fapll_set_div_mult(rate, parent_rate,
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&pre_div_p, &mult_n);
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if (error)
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return error;
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ti_fapll_set_bypass(fd);
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v = readl_relaxed(fd->base);
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v &= ~FAPLL_MAIN_CLEAR_MASK;
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v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
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v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
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writel_relaxed(v, fd->base);
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if (ti_fapll_is_enabled(hw))
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ti_fapll_wait_lock(fd);
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ti_fapll_clear_bypass(fd);
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return 0;
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}
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static struct clk_ops ti_fapll_ops = {
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.enable = ti_fapll_enable,
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.disable = ti_fapll_disable,
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.is_enabled = ti_fapll_is_enabled,
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.recalc_rate = ti_fapll_recalc_rate,
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.get_parent = ti_fapll_get_parent,
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.round_rate = ti_fapll_round_rate,
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.set_rate = ti_fapll_set_rate,
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};
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static int ti_fapll_synth_enable(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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v &= ~(1 << synth->index);
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writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
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return 0;
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}
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static void ti_fapll_synth_disable(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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v |= 1 << synth->index;
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writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
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}
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static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
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return !(v & (1 << synth->index));
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}
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/*
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* See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
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*/
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static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct fapll_synth *synth = to_synth(hw);
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u32 synth_div_m;
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long long rate;
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/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
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if (!synth->div)
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return 32768;
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/*
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* PLL in bypass sets the synths in bypass mode too. The PLL rate
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* can be also be set to 27MHz, so we can't use parent_rate to
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* check for bypass mode.
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*/
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if (ti_fapll_clock_is_bypass(synth->fd))
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return parent_rate;
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rate = parent_rate;
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/*
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* Synth frequency integer and fractional divider.
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* Note that the phase output K is 8, so the result needs
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* to be multiplied by SYNTH_PHASE_K.
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*/
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if (synth->freq) {
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u32 v, synth_int_div, synth_frac_div, synth_div_freq;
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v = readl_relaxed(synth->freq);
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synth_int_div = (v >> 24) & 0xf;
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synth_frac_div = v & 0xffffff;
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synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
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rate *= 10000000;
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do_div(rate, synth_div_freq);
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rate *= SYNTH_PHASE_K;
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}
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/* Synth post-divider M */
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synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
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return DIV_ROUND_UP_ULL(rate, synth_div_m);
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}
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static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct fapll_synth *synth = to_synth(hw);
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unsigned long current_rate, frac_rate;
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u32 post_div_m;
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current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
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post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
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frac_rate = current_rate * post_div_m;
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return frac_rate;
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}
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static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
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unsigned long rate,
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unsigned long parent_rate)
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{
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u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
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post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
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post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
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if (post_div_m > SYNTH_MAX_DIV_M)
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return -EINVAL;
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if (!post_div_m)
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post_div_m = 1;
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for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
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synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
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SYNTH_PHASE_K *
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10000000,
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rate * post_div_m);
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synth_frac_div = synth_int_div % 10000000;
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synth_int_div /= 10000000;
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if (synth_int_div <= SYNTH_MAX_INT_DIV)
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break;
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}
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if (synth_int_div > SYNTH_MAX_INT_DIV)
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return -EINVAL;
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v = readl_relaxed(synth->freq);
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v &= ~0x1fffffff;
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v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
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v |= (synth_frac_div & 0xffffff);
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v |= SYNTH_LDFREQ;
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writel_relaxed(v, synth->freq);
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return post_div_m;
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}
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static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct fapll_synth *synth = to_synth(hw);
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struct fapll_data *fd = synth->fd;
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unsigned long r;
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if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
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return -EINVAL;
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/* Only post divider m available with no fractional divider? */
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if (!synth->freq) {
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unsigned long frac_rate;
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u32 synth_post_div_m;
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frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
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synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
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r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
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goto out;
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}
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r = *parent_rate * SYNTH_PHASE_K;
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if (rate > r)
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goto out;
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r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
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if (rate < r)
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goto out;
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r = rate;
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out:
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return r;
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}
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static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct fapll_synth *synth = to_synth(hw);
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struct fapll_data *fd = synth->fd;
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unsigned long frac_rate, post_rate = 0;
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u32 post_div_m = 0, v;
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if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
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return -EINVAL;
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/* Produce the rate with just post divider M? */
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frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
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if (frac_rate < rate) {
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if (!synth->freq)
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return -EINVAL;
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} else {
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post_div_m = DIV_ROUND_UP(frac_rate, rate);
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if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
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post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
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if (!synth->freq && !post_rate)
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return -EINVAL;
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}
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/* Need to recalculate the fractional divider? */
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if ((post_rate != rate) && synth->freq)
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post_div_m = ti_fapll_synth_set_frac_rate(synth,
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rate,
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parent_rate);
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v = readl_relaxed(synth->div);
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v &= ~SYNTH_MAX_DIV_M;
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v |= post_div_m;
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v |= SYNTH_LDMDIV1;
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writel_relaxed(v, synth->div);
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return 0;
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}
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static struct clk_ops ti_fapll_synt_ops = {
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.enable = ti_fapll_synth_enable,
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.disable = ti_fapll_synth_disable,
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.is_enabled = ti_fapll_synth_is_enabled,
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.recalc_rate = ti_fapll_synth_recalc_rate,
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.round_rate = ti_fapll_synth_round_rate,
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.set_rate = ti_fapll_synth_set_rate,
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};
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static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
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void __iomem *freq,
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void __iomem *div,
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int index,
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const char *name,
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const char *parent,
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struct clk *pll_clk)
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|
{
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struct clk_init_data *init;
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struct fapll_synth *synth;
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|
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init = kzalloc(sizeof(*init), GFP_KERNEL);
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if (!init)
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return ERR_PTR(-ENOMEM);
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|
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init->ops = &ti_fapll_synt_ops;
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init->name = name;
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init->parent_names = &parent;
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init->num_parents = 1;
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|
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synth = kzalloc(sizeof(*synth), GFP_KERNEL);
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if (!synth)
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goto free;
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|
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synth->fd = fd;
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synth->index = index;
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synth->freq = freq;
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synth->div = div;
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synth->name = name;
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synth->hw.init = init;
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synth->clk_pll = pll_clk;
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return clk_register(NULL, &synth->hw);
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|
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free:
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kfree(synth);
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kfree(init);
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|
|
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return ERR_PTR(-ENOMEM);
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}
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|
|
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static void __init ti_fapll_setup(struct device_node *node)
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{
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struct fapll_data *fd;
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struct clk_init_data *init = NULL;
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const char *parent_name[2];
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struct clk *pll_clk;
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int i;
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|
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd)
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return;
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|
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fd->outputs.clks = kzalloc(sizeof(struct clk *) *
|
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MAX_FAPLL_OUTPUTS + 1,
|
|
GFP_KERNEL);
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|
if (!fd->outputs.clks)
|
|
goto free;
|
|
|
|
init = kzalloc(sizeof(*init), GFP_KERNEL);
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|
if (!init)
|
|
goto free;
|
|
|
|
init->ops = &ti_fapll_ops;
|
|
init->name = node->name;
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|
|
|
init->num_parents = of_clk_get_parent_count(node);
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|
if (init->num_parents != 2) {
|
|
pr_err("%s must have two parents\n", node->name);
|
|
goto free;
|
|
}
|
|
|
|
of_clk_parent_fill(node, parent_name, 2);
|
|
init->parent_names = parent_name;
|
|
|
|
fd->clk_ref = of_clk_get(node, 0);
|
|
if (IS_ERR(fd->clk_ref)) {
|
|
pr_err("%s could not get clk_ref\n", node->name);
|
|
goto free;
|
|
}
|
|
|
|
fd->clk_bypass = of_clk_get(node, 1);
|
|
if (IS_ERR(fd->clk_bypass)) {
|
|
pr_err("%s could not get clk_bypass\n", node->name);
|
|
goto free;
|
|
}
|
|
|
|
fd->base = of_iomap(node, 0);
|
|
if (!fd->base) {
|
|
pr_err("%s could not get IO base\n", node->name);
|
|
goto free;
|
|
}
|
|
|
|
if (fapll_is_ddr_pll(fd->base))
|
|
fd->bypass_bit_inverted = true;
|
|
|
|
fd->name = node->name;
|
|
fd->hw.init = init;
|
|
|
|
/* Register the parent PLL */
|
|
pll_clk = clk_register(NULL, &fd->hw);
|
|
if (IS_ERR(pll_clk))
|
|
goto unmap;
|
|
|
|
fd->outputs.clks[0] = pll_clk;
|
|
fd->outputs.clk_num++;
|
|
|
|
/*
|
|
* Set up the child synthesizers starting at index 1 as the
|
|
* PLL output is at index 0. We need to check the clock-indices
|
|
* for numbering in case there are holes in the synth mapping,
|
|
* and then probe the synth register to see if it has a FREQ
|
|
* register available.
|
|
*/
|
|
for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
|
|
const char *output_name;
|
|
void __iomem *freq, *div;
|
|
struct clk *synth_clk;
|
|
int output_instance;
|
|
u32 v;
|
|
|
|
if (of_property_read_string_index(node, "clock-output-names",
|
|
i, &output_name))
|
|
continue;
|
|
|
|
if (of_property_read_u32_index(node, "clock-indices", i,
|
|
&output_instance))
|
|
output_instance = i;
|
|
|
|
freq = fd->base + (output_instance * 8);
|
|
div = freq + 4;
|
|
|
|
/* Check for hardwired audio_pll_clk1 */
|
|
if (is_audio_pll_clk1(freq)) {
|
|
freq = NULL;
|
|
div = NULL;
|
|
} else {
|
|
/* Does the synthesizer have a FREQ register? */
|
|
v = readl_relaxed(freq);
|
|
if (!v)
|
|
freq = NULL;
|
|
}
|
|
synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
|
|
output_name, node->name,
|
|
pll_clk);
|
|
if (IS_ERR(synth_clk))
|
|
continue;
|
|
|
|
fd->outputs.clks[output_instance] = synth_clk;
|
|
fd->outputs.clk_num++;
|
|
|
|
clk_register_clkdev(synth_clk, output_name, NULL);
|
|
}
|
|
|
|
/* Register the child synthesizers as the FAPLL outputs */
|
|
of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
|
|
/* Add clock alias for the outputs */
|
|
|
|
kfree(init);
|
|
|
|
return;
|
|
|
|
unmap:
|
|
iounmap(fd->base);
|
|
free:
|
|
if (fd->clk_bypass)
|
|
clk_put(fd->clk_bypass);
|
|
if (fd->clk_ref)
|
|
clk_put(fd->clk_ref);
|
|
kfree(fd->outputs.clks);
|
|
kfree(fd);
|
|
kfree(init);
|
|
}
|
|
|
|
CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);
|