![Tony Lindgren](/assets/img/avatar_default.png)
Conflicts: arch/arm/mach-omap2/board-omap3logic.c arch/arm/mach-omap2/gpmc.c drivers/media/platform/omap/omap_vout.c drivers/media/platform/omap/omap_vout_vrfb.c
761 lines
20 KiB
C
761 lines
20 KiB
C
/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <trace/events/power.h>
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#include <asm/suspend.h>
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#include <asm/system_misc.h>
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#include <plat/sram.h>
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#include "clockdomain.h"
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#include "powerdomain.h"
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#include <plat/prcm.h>
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#include <plat-omap/dma-omap.h>
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#include "common.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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#include "gpmc.h"
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#include "prm-regbits-34xx.h"
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#include "prm2xxx_3xxx.h"
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#include "pm.h"
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#include "sdrc.h"
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#include "control.h"
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/* pm34xx errata defined in pm.h */
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u16 pm34xx_errata;
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
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#ifdef CONFIG_SUSPEND
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u32 saved_state;
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#endif
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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static int (*_omap_save_secure_sram)(u32 *addr);
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void (*omap3_do_wfi_sram)(void);
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
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static struct powerdomain *core_pwrdm, *per_pwrdm;
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static void omap3_core_save_context(void)
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{
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omap3_ctrl_save_padconf();
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/*
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* Force write last pad into memory, as this can fail in some
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* cases according to errata 1.157, 1.185
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*/
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omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
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OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
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/* Save the Interrupt controller context */
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omap_intc_save_context();
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/* Save the GPMC context */
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
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omap_dma_global_context_save();
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}
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static void omap3_core_restore_context(void)
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{
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/* Restore the control module context, padconf restored by h/w */
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omap3_control_restore_context();
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/* Restore the GPMC context */
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
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omap_dma_global_context_restore();
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}
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/*
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* FIXME: This function should be called before entering off-mode after
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* OMAP3 secure services have been accessed. Currently it is only called
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* once during boot sequence, but this works as we are not using secure
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* services.
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*/
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static void omap3_save_secure_ram_context(void)
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{
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u32 ret;
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int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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/*
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* MPU next state must be set to POWER_ON temporarily,
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* otherwise the WFI executed inside the ROM code
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* will hang the system.
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*/
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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ret = _omap_save_secure_sram((u32 *)
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__pa(omap3_secure_ram_storage));
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pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
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/* Following is for error tracking, it should not happen */
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if (ret) {
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pr_err("save_secure_sram() returns %08x\n", ret);
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while (1)
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;
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}
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}
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}
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/*
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
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{
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u32 wkst, fclk, iclk, clken;
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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int c = 0;
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
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wkst &= ~ignore_bits;
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if (wkst) {
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iclk = omap2_cm_read_mod_reg(module, iclk_off);
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fclk = omap2_cm_read_mod_reg(module, fclk_off);
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while (wkst) {
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clken = wkst;
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omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
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/*
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* For USBHOST, we don't know whether HOST1 or
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* HOST2 woke us up, so enable both f-clocks
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*/
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if (module == OMAP3430ES2_USBHOST_MOD)
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
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omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
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omap2_prm_write_mod_reg(wkst, module, wkst_off);
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= ~ignore_bits;
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c++;
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}
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omap2_cm_write_mod_reg(iclk, module, iclk_off);
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omap2_cm_write_mod_reg(fclk, module, fclk_off);
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}
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return c;
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}
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static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
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{
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int c;
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
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return c ? IRQ_HANDLED : IRQ_NONE;
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}
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static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
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{
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int c;
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/*
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* Clear all except ST_IO and ST_IO_CHAIN for wkup module,
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* these are handled in a separate handler to avoid acking
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* IO events before parsing in mux code
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*/
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
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c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
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}
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return c ? IRQ_HANDLED : IRQ_NONE;
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}
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static void omap34xx_save_context(u32 *save)
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{
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u32 val;
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/* Read Auxiliary Control Register */
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
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*save++ = 1;
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*save++ = val;
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/* Read L2 AUX ctrl register */
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asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
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*save++ = 1;
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*save++ = val;
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}
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static int omap34xx_do_sram_idle(unsigned long save_state)
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{
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omap34xx_cpu_suspend(save_state);
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return 0;
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}
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void omap_sram_idle(void)
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{
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/* Variable to tell what needs to be saved and restored
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* in omap_sram_idle*/
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/* save_state = 0 => Nothing to save and restored */
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/* save_state = 1 => Only L1 and logic lost */
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/* save_state = 2 => Only L2 lost */
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/* save_state = 3 => L1, L2 and logic lost */
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int save_state = 0;
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int mpu_next_state = PWRDM_POWER_ON;
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int per_next_state = PWRDM_POWER_ON;
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int core_next_state = PWRDM_POWER_ON;
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int per_going_off;
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int core_prev_state;
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u32 sdrc_pwr = 0;
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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switch (mpu_next_state) {
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case PWRDM_POWER_ON:
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case PWRDM_POWER_RET:
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/* No need to save context */
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save_state = 0;
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break;
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case PWRDM_POWER_OFF:
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save_state = 3;
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break;
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default:
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/* Invalid state */
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pr_err("Invalid mpu state in sram_idle\n");
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return;
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}
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/* NEON control */
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if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
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pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
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/* Enable IO-PAD and IO-CHAIN wakeups */
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per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
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core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
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pwrdm_pre_transition(NULL);
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/* PER */
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if (per_next_state < PWRDM_POWER_ON) {
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per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
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omap2_gpio_prepare_for_idle(per_going_off);
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}
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/* CORE */
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if (core_next_state < PWRDM_POWER_ON) {
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if (core_next_state == PWRDM_POWER_OFF) {
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omap3_core_save_context();
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omap3_cm_save_context();
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}
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}
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omap3_intc_prepare_idle();
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/*
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* On EMU/HS devices ROM code restores a SRDC value
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* from scratchpad which has automatic self refresh on timeout
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* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
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* Hence store/restore the SDRC_POWER register here.
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*/
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if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
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(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
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omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
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core_next_state == PWRDM_POWER_OFF)
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sdrc_pwr = sdrc_read_reg(SDRC_POWER);
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/*
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* omap3_arm_context is the location where some ARM context
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* get saved. The rest is placed on the stack, and restored
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* from there before resuming.
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*/
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if (save_state)
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omap34xx_save_context(omap3_arm_context);
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if (save_state == 1 || save_state == 3)
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cpu_suspend(save_state, omap34xx_do_sram_idle);
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else
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omap34xx_do_sram_idle(save_state);
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/* Restore normal SDRC POWER settings */
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if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
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(omap_type() == OMAP2_DEVICE_TYPE_EMU ||
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omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
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core_next_state == PWRDM_POWER_OFF)
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sdrc_write_reg(sdrc_pwr, SDRC_POWER);
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/* CORE */
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if (core_next_state < PWRDM_POWER_ON) {
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core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
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if (core_prev_state == PWRDM_POWER_OFF) {
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omap3_core_restore_context();
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omap3_cm_restore_context();
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omap3_sram_restore_context();
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omap2_sms_restore_context();
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}
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if (core_next_state == PWRDM_POWER_OFF)
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omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
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OMAP3430_GR_MOD,
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OMAP3_PRM_VOLTCTRL_OFFSET);
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}
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omap3_intc_resume_idle();
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pwrdm_post_transition(NULL);
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/* PER */
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if (per_next_state < PWRDM_POWER_ON)
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omap2_gpio_resume_after_idle();
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}
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static void omap3_pm_idle(void)
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{
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local_fiq_disable();
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if (omap_irq_pending())
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goto out;
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trace_power_start(POWER_CSTATE, 1, smp_processor_id());
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trace_cpu_idle(1, smp_processor_id());
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omap_sram_idle();
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trace_power_end(smp_processor_id());
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trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
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out:
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local_fiq_enable();
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}
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#ifdef CONFIG_SUSPEND
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static int omap3_pm_suspend(void)
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{
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struct power_state *pwrst;
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int state, ret = 0;
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/* Read current next_pwrsts */
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list_for_each_entry(pwrst, &pwrst_list, node)
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pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
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/* Set ones wanted by suspend */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
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goto restore;
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if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
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goto restore;
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}
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omap3_intc_suspend();
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omap_sram_idle();
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restore:
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/* Restore next_pwrsts */
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list_for_each_entry(pwrst, &pwrst_list, node) {
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state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
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if (state > pwrst->next_state) {
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pr_info("Powerdomain (%s) didn't enter target state %d\n",
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pwrst->pwrdm->name, pwrst->next_state);
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ret = -1;
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}
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omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
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}
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if (ret)
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pr_err("Could not enter target state in pm_suspend\n");
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else
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pr_info("Successfully put all powerdomains to target state\n");
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return ret;
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}
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#endif /* CONFIG_SUSPEND */
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/**
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* omap3_iva_idle(): ensure IVA is in idle so it can be put into
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* retention
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*
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* In cases where IVA2 is activated by bootcode, it may prevent
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* full-chip retention or off-mode because it is not idle. This
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* function forces the IVA2 into idle state so it can go
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* into retention/off and thus allow full-chip retention/off.
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*
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**/
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static void __init omap3_iva_idle(void)
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{
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/* ensure IVA2 clock is disabled */
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omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* if no clock activity, nothing else to do */
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if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
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OMAP3430_CLKACTIVITY_IVA2_MASK))
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return;
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/* Reset IVA2 */
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omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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OMAP3430_RST2_IVA2_MASK |
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OMAP3430_RST3_IVA2_MASK,
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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/* Enable IVA2 clock */
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omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
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OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* Set IVA2 boot mode to 'idle' */
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omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
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OMAP343X_CONTROL_IVA2_BOOTMOD);
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/* Un-reset IVA2 */
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omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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/* Disable IVA2 clock */
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omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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/* Reset IVA2 */
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omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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OMAP3430_RST2_IVA2_MASK |
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OMAP3430_RST3_IVA2_MASK,
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OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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}
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static void __init omap3_d2d_idle(void)
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{
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u16 mask, padconf;
|
|
|
|
/* In a stand alone OMAP3430 where there is not a stacked
|
|
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
|
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
|
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
|
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
padconf |= mask;
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
padconf |= mask;
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
/* reset modem */
|
|
omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
|
CORE_MOD, OMAP2_RM_RSTCTRL);
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
|
}
|
|
|
|
static void __init prcm_setup_regs(void)
|
|
{
|
|
u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
|
|
OMAP3630_EN_UART4_MASK : 0;
|
|
u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
|
|
OMAP3630_GRPSEL_UART4_MASK : 0;
|
|
|
|
/* XXX This should be handled by hwmod code or SCM init code */
|
|
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
|
|
|
/*
|
|
* Enable control of expternal oscillator through
|
|
* sys_clkreq. In the long run clock framework should
|
|
* take care of this.
|
|
*/
|
|
omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
|
OMAP3430_GR_MOD,
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
|
|
|
/* setup wakup source */
|
|
omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
|
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
|
WKUP_MOD, PM_WKEN);
|
|
/* No need to write EN_IO, that is always enabled */
|
|
omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
|
OMAP3430_GRPSEL_GPT1_MASK |
|
|
OMAP3430_GRPSEL_GPT12_MASK,
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
/* Enable PM_WKEN to support DSS LPR */
|
|
omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
|
OMAP3430_DSS_MOD, PM_WKEN);
|
|
|
|
/* Enable wakeups in PER */
|
|
omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
|
|
OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
|
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
|
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
|
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
|
OMAP3430_EN_MCBSP4_MASK,
|
|
OMAP3430_PER_MOD, PM_WKEN);
|
|
/* and allow them to wake up MPU */
|
|
omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
|
|
OMAP3430_GRPSEL_GPIO2_MASK |
|
|
OMAP3430_GRPSEL_GPIO3_MASK |
|
|
OMAP3430_GRPSEL_GPIO4_MASK |
|
|
OMAP3430_GRPSEL_GPIO5_MASK |
|
|
OMAP3430_GRPSEL_GPIO6_MASK |
|
|
OMAP3430_GRPSEL_UART3_MASK |
|
|
OMAP3430_GRPSEL_MCBSP2_MASK |
|
|
OMAP3430_GRPSEL_MCBSP3_MASK |
|
|
OMAP3430_GRPSEL_MCBSP4_MASK,
|
|
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
/* Don't attach IVA interrupts */
|
|
if (omap3_has_iva()) {
|
|
omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
|
|
OMAP3430_PM_IVAGRPSEL);
|
|
}
|
|
|
|
/* Clear any pending 'reset' flags */
|
|
omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
|
omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
|
|
|
/* Clear any pending PRCM interrupts */
|
|
omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
if (omap3_has_iva())
|
|
omap3_iva_idle();
|
|
|
|
omap3_d2d_idle();
|
|
}
|
|
|
|
void omap3_pm_off_mode_enable(int enable)
|
|
{
|
|
struct power_state *pwrst;
|
|
u32 state;
|
|
|
|
if (enable)
|
|
state = PWRDM_POWER_OFF;
|
|
else
|
|
state = PWRDM_POWER_RET;
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
|
|
pwrst->pwrdm == core_pwrdm &&
|
|
state == PWRDM_POWER_OFF) {
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
pr_warn("%s: Core OFF disabled due to errata i583\n",
|
|
__func__);
|
|
} else {
|
|
pwrst->next_state = state;
|
|
}
|
|
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
}
|
|
}
|
|
|
|
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (pwrst->pwrdm == pwrdm)
|
|
return pwrst->next_state;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
if (pwrst->pwrdm == pwrdm) {
|
|
pwrst->next_state = state;
|
|
return 0;
|
|
}
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
|
{
|
|
struct power_state *pwrst;
|
|
|
|
if (!pwrdm->pwrsts)
|
|
return 0;
|
|
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
|
|
if (!pwrst)
|
|
return -ENOMEM;
|
|
pwrst->pwrdm = pwrdm;
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
list_add(&pwrst->node, &pwrst_list);
|
|
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
|
|
|
return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
}
|
|
|
|
/*
|
|
* Push functions to SRAM
|
|
*
|
|
* The minimum set of functions is pushed to SRAM for execution:
|
|
* - omap3_do_wfi for erratum i581 WA,
|
|
* - save_secure_ram_context for security extensions.
|
|
*/
|
|
void omap_push_sram_idle(void)
|
|
{
|
|
omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
|
|
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
|
|
_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
|
|
save_secure_ram_context_sz);
|
|
}
|
|
|
|
static void __init pm_errata_configure(void)
|
|
{
|
|
if (cpu_is_omap3630()) {
|
|
pm34xx_errata |= PM_RTA_ERRATUM_i608;
|
|
/* Enable the l2 cache toggling in sleep logic */
|
|
enable_omap3630_toggle_l2_on_restore();
|
|
if (omap_rev() < OMAP3630_REV_ES1_2)
|
|
pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
|
|
}
|
|
}
|
|
|
|
int __init omap3_pm_init(void)
|
|
{
|
|
struct power_state *pwrst, *tmp;
|
|
struct clockdomain *neon_clkdm, *mpu_clkdm;
|
|
int ret;
|
|
|
|
if (!omap3_has_io_chain_ctrl())
|
|
pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
|
|
|
|
pm_errata_configure();
|
|
|
|
/* XXX prcm_setup_regs needs to be before enabling hw
|
|
* supervised mode for powerdomains */
|
|
prcm_setup_regs();
|
|
|
|
ret = request_irq(omap_prcm_event_to_irq("wkup"),
|
|
_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
|
|
|
|
if (ret) {
|
|
pr_err("pm: Failed to request pm_wkup irq\n");
|
|
goto err1;
|
|
}
|
|
|
|
/* IO interrupt is shared with mux code */
|
|
ret = request_irq(omap_prcm_event_to_irq("io"),
|
|
_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
|
|
omap3_pm_init);
|
|
enable_irq(omap_prcm_event_to_irq("io"));
|
|
|
|
if (ret) {
|
|
pr_err("pm: Failed to request pm_io irq\n");
|
|
goto err2;
|
|
}
|
|
|
|
ret = pwrdm_for_each(pwrdms_setup, NULL);
|
|
if (ret) {
|
|
pr_err("Failed to setup powerdomains\n");
|
|
goto err3;
|
|
}
|
|
|
|
(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
|
|
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
|
if (mpu_pwrdm == NULL) {
|
|
pr_err("Failed to get mpu_pwrdm\n");
|
|
ret = -EINVAL;
|
|
goto err3;
|
|
}
|
|
|
|
neon_pwrdm = pwrdm_lookup("neon_pwrdm");
|
|
per_pwrdm = pwrdm_lookup("per_pwrdm");
|
|
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
|
|
|
neon_clkdm = clkdm_lookup("neon_clkdm");
|
|
mpu_clkdm = clkdm_lookup("mpu_clkdm");
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
omap_pm_suspend = omap3_pm_suspend;
|
|
#endif
|
|
|
|
arm_pm_idle = omap3_pm_idle;
|
|
omap3_idle_init();
|
|
|
|
/*
|
|
* RTA is disabled during initialization as per erratum i608
|
|
* it is safer to disable RTA by the bootloader, but we would like
|
|
* to be doubly sure here and prevent any mishaps.
|
|
*/
|
|
if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
|
|
omap3630_ctrl_disable_rta();
|
|
|
|
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
|
|
omap3_secure_ram_storage =
|
|
kmalloc(0x803F, GFP_KERNEL);
|
|
if (!omap3_secure_ram_storage)
|
|
pr_err("Memory allocation failed when allocating for secure sram context\n");
|
|
|
|
local_irq_disable();
|
|
local_fiq_disable();
|
|
|
|
omap_dma_global_context_save();
|
|
omap3_save_secure_ram_context();
|
|
omap_dma_global_context_restore();
|
|
|
|
local_irq_enable();
|
|
local_fiq_enable();
|
|
}
|
|
|
|
omap3_save_scratchpad_contents();
|
|
return ret;
|
|
|
|
err3:
|
|
list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
|
|
list_del(&pwrst->node);
|
|
kfree(pwrst);
|
|
}
|
|
free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
|
|
err2:
|
|
free_irq(omap_prcm_event_to_irq("wkup"), NULL);
|
|
err1:
|
|
return ret;
|
|
}
|