![Christophe Leroy](/assets/img/avatar_default.png)
Initially, a NAPI TX routine has been implemented separately from NAPI RX, as done on the freescale/gianfar driver. By merging NAPI RX and NAPI TX, we reduce the amount of TX completion interrupts. Handling of the budget in association with TX interrupts is based on indications provided at https://wiki.linuxfoundation.org/networking/napi We never proceed more than the complete TX ring on a single run. At the same time, we fix an issue in the handling of fep->tx_free: It is only when fep->tx_free goes up to MAX_SKB_FRAGS that we need to wake up the queue. There is no need to call netif_wake_queue() at every packet successfully transmitted. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
244 lines
7.6 KiB
C
244 lines
7.6 KiB
C
#ifndef FS_ENET_H
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#define FS_ENET_H
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#include <linux/mii.h>
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#include <linux/netdevice.h>
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#include <linux/types.h>
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#include <linux/list.h>
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#include <linux/phy.h>
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#include <linux/dma-mapping.h>
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#include <linux/fs_enet_pd.h>
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#include <asm/fs_pd.h>
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#ifdef CONFIG_CPM1
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#include <asm/cpm1.h>
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#endif
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#if defined(CONFIG_FS_ENET_HAS_FEC)
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#include <asm/cpm.h>
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#if defined(CONFIG_FS_ENET_MPC5121_FEC)
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/* MPC5121 FEC has different register layout */
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struct fec {
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u32 fec_reserved0;
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u32 fec_ievent; /* Interrupt event reg */
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u32 fec_imask; /* Interrupt mask reg */
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u32 fec_reserved1;
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u32 fec_r_des_active; /* Receive descriptor reg */
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u32 fec_x_des_active; /* Transmit descriptor reg */
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u32 fec_reserved2[3];
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u32 fec_ecntrl; /* Ethernet control reg */
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u32 fec_reserved3[6];
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u32 fec_mii_data; /* MII manage frame reg */
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u32 fec_mii_speed; /* MII speed control reg */
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u32 fec_reserved4[7];
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u32 fec_mib_ctrlstat; /* MIB control/status reg */
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u32 fec_reserved5[7];
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u32 fec_r_cntrl; /* Receive control reg */
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u32 fec_reserved6[15];
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u32 fec_x_cntrl; /* Transmit Control reg */
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u32 fec_reserved7[7];
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u32 fec_addr_low; /* Low 32bits MAC address */
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u32 fec_addr_high; /* High 16bits MAC address */
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u32 fec_opd; /* Opcode + Pause duration */
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u32 fec_reserved8[10];
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u32 fec_hash_table_high; /* High 32bits hash table */
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u32 fec_hash_table_low; /* Low 32bits hash table */
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u32 fec_grp_hash_table_high; /* High 32bits hash table */
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u32 fec_grp_hash_table_low; /* Low 32bits hash table */
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u32 fec_reserved9[7];
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u32 fec_x_wmrk; /* FIFO transmit water mark */
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u32 fec_reserved10;
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u32 fec_r_bound; /* FIFO receive bound reg */
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u32 fec_r_fstart; /* FIFO receive start reg */
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u32 fec_reserved11[11];
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u32 fec_r_des_start; /* Receive descriptor ring */
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u32 fec_x_des_start; /* Transmit descriptor ring */
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u32 fec_r_buff_size; /* Maximum receive buff size */
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u32 fec_reserved12[26];
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u32 fec_dma_control; /* DMA Endian and other ctrl */
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};
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#endif
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struct fec_info {
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struct fec __iomem *fecp;
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u32 mii_speed;
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};
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#endif
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#ifdef CONFIG_CPM2
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#include <asm/cpm2.h>
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#endif
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/* hw driver ops */
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struct fs_ops {
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int (*setup_data)(struct net_device *dev);
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int (*allocate_bd)(struct net_device *dev);
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void (*free_bd)(struct net_device *dev);
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void (*cleanup_data)(struct net_device *dev);
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void (*set_multicast_list)(struct net_device *dev);
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void (*adjust_link)(struct net_device *dev);
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void (*restart)(struct net_device *dev);
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void (*stop)(struct net_device *dev);
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void (*napi_clear_event)(struct net_device *dev);
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void (*napi_enable)(struct net_device *dev);
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void (*napi_disable)(struct net_device *dev);
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void (*rx_bd_done)(struct net_device *dev);
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void (*tx_kickstart)(struct net_device *dev);
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u32 (*get_int_events)(struct net_device *dev);
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void (*clear_int_events)(struct net_device *dev, u32 int_events);
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void (*ev_error)(struct net_device *dev, u32 int_events);
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int (*get_regs)(struct net_device *dev, void *p, int *sizep);
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int (*get_regs_len)(struct net_device *dev);
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void (*tx_restart)(struct net_device *dev);
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};
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struct phy_info {
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unsigned int id;
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const char *name;
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void (*startup) (struct net_device * dev);
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void (*shutdown) (struct net_device * dev);
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void (*ack_int) (struct net_device * dev);
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};
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/* The FEC stores dest/src/type, data, and checksum for receive packets.
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*/
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#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
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#define MIN_MTU 46 /* this is data size */
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#define CRC_LEN 4
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#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
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#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
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/* Must be a multiple of 32 (to cover both FEC & FCC) */
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#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31)
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/* This is needed so that invalidate_xxx wont invalidate too much */
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#define ENET_RX_ALIGN 16
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#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
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struct fs_enet_private {
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struct napi_struct napi;
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struct device *dev; /* pointer back to the device (must be initialized first) */
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struct net_device *ndev;
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spinlock_t lock; /* during all ops except TX pckt processing */
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spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */
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struct fs_platform_info *fpi;
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const struct fs_ops *ops;
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int rx_ring, tx_ring;
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dma_addr_t ring_mem_addr;
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void __iomem *ring_base;
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struct sk_buff **rx_skbuff;
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struct sk_buff **tx_skbuff;
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char *mapped_as_page;
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cbd_t __iomem *rx_bd_base; /* Address of Rx and Tx buffers. */
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cbd_t __iomem *tx_bd_base;
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cbd_t __iomem *dirty_tx; /* ring entries to be free()ed. */
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cbd_t __iomem *cur_rx;
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cbd_t __iomem *cur_tx;
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int tx_free;
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struct net_device_stats stats;
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struct timer_list phy_timer_list;
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const struct phy_info *phy;
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u32 msg_enable;
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struct mii_if_info mii_if;
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unsigned int last_mii_status;
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int interrupt;
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int oldduplex, oldspeed, oldlink; /* current settings */
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/* event masks */
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u32 ev_napi; /* mask of NAPI events */
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u32 ev; /* event mask */
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u32 ev_err; /* error event mask */
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u16 bd_rx_empty; /* mask of BD rx empty */
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u16 bd_rx_err; /* mask of BD rx errors */
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union {
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struct {
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int idx; /* FEC1 = 0, FEC2 = 1 */
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void __iomem *fecp; /* hw registers */
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u32 hthi, htlo; /* state for multicast */
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} fec;
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struct {
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int idx; /* FCC1-3 = 0-2 */
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void __iomem *fccp; /* hw registers */
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void __iomem *ep; /* parameter ram */
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void __iomem *fcccp; /* hw registers cont. */
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void __iomem *mem; /* FCC DPRAM */
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u32 gaddrh, gaddrl; /* group address */
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} fcc;
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struct {
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int idx; /* FEC1 = 0, FEC2 = 1 */
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void __iomem *sccp; /* hw registers */
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void __iomem *ep; /* parameter ram */
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u32 hthi, htlo; /* state for multicast */
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} scc;
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};
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};
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/***************************************************************************/
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void fs_init_bds(struct net_device *dev);
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void fs_cleanup_bds(struct net_device *dev);
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/***************************************************************************/
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#define DRV_MODULE_NAME "fs_enet"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "1.1"
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#define DRV_MODULE_RELDATE "Sep 22, 2014"
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/***************************************************************************/
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int fs_enet_platform_init(void);
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void fs_enet_platform_cleanup(void);
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/***************************************************************************/
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/* buffer descriptor access macros */
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/* access macros */
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#if defined(CONFIG_CPM1)
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/* for a a CPM1 __raw_xxx's are sufficient */
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#define __cbd_out32(addr, x) __raw_writel(x, addr)
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#define __cbd_out16(addr, x) __raw_writew(x, addr)
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#define __cbd_in32(addr) __raw_readl(addr)
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#define __cbd_in16(addr) __raw_readw(addr)
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#else
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/* for others play it safe */
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#define __cbd_out32(addr, x) out_be32(addr, x)
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#define __cbd_out16(addr, x) out_be16(addr, x)
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#define __cbd_in32(addr) in_be32(addr)
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#define __cbd_in16(addr) in_be16(addr)
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#endif
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/* write */
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#define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc))
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#define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
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#define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
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/* read */
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#define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc)
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#define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen)
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#define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr)
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/* set bits */
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#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
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/* clear bits */
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#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
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/*******************************************************************/
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extern const struct fs_ops fs_fec_ops;
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extern const struct fs_ops fs_fcc_ops;
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extern const struct fs_ops fs_scc_ops;
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/*******************************************************************/
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#endif
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