1793331e09
There is no reason in rx_descs property because davinici_cpdma driver splits pool of descriptors equally between tx and rx channels. That is, if number of descriptors 256, 128 of them are for rx channels. While receiving, the descriptor is freed to the pool and then allocated with new skb. And if in DT the "rx_descs" is set to 64, then 128 - 64 = 64 descriptors are always in the pool and cannot be used, for tx, for instance. It's not correct resource usage, better to set it to half of pool, then the rx pool can be used in full. It will not have any impact on performance, as anyway, the "redundant" descriptors were unused. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/* Texas Instruments Ethernet Switch Driver
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*
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* Copyright (C) 2013 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __CPSW_H__
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#define __CPSW_H__
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#include <linux/if_ether.h>
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#include <linux/phy.h>
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struct cpsw_slave_data {
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struct device_node *phy_node;
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char phy_id[MII_BUS_ID_SIZE];
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int phy_if;
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u8 mac_addr[ETH_ALEN];
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u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
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};
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struct cpsw_platform_data {
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struct cpsw_slave_data *slave_data;
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u32 ss_reg_ofs; /* Subsystem control register offset */
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u32 channels; /* number of cpdma channels (symmetric) */
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u32 slaves; /* number of slave cpgmac ports */
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u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
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u32 cpts_clock_mult; /* convert input clock ticks to nanoseconds */
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u32 cpts_clock_shift; /* convert input clock ticks to nanoseconds */
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u32 ale_entries; /* ale table size */
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u32 bd_ram_size; /*buffer descriptor ram size */
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u32 mac_control; /* Mac control register */
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u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
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bool dual_emac; /* Enable Dual EMAC mode */
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};
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void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave);
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int ti_cm_get_macid(struct device *dev, int slave, u8 *mac_addr);
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#endif /* __CPSW_H__ */
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