1623ad8ec0
LAN8814 is a low-power, quad-port triple-speed (10BASE-T/100BASETX/1000BASE-T) Ethernet physical layer transceiver (PHY). It supports transmission and reception of data on standard CAT-5, as well as CAT-5e and CAT-6, unshielded twisted pair (UTP) cables. LAN8814 supports industry-standard QSGMII (Quad Serial Gigabit Media Independent Interface) and Q-USGMII (Quad Universal Serial Gigabit Media Independent Interface) providing chip-to-chip connection to four Gigabit Ethernet MACs using a single serialized link (differential pair) in each direction. The LAN8814 SKU supports high-accuracy timestamping functions to support IEEE-1588 solutions using Microchip Ethernet switches, as well as customer solutions based on SoCs and FPGAs. The LAN8804 SKU has same features as that of LAN8814 SKU except that it does not support 1588, SyncE, or Q-USGMII with PCH/MCH. This adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T, QSGMII link with the MAC. Signed-off-by: Divya Koppera<divya.koppera@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/linux/micrel_phy.h
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*
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* Micrel PHY IDs
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*/
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#ifndef _MICREL_PHY_H
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#define _MICREL_PHY_H
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#define MICREL_PHY_ID_MASK 0x00fffff0
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#define PHY_ID_KSZ8873MLL 0x000e7237
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#define PHY_ID_KSZ9021 0x00221610
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#define PHY_ID_KSZ9021RLRN 0x00221611
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#define PHY_ID_KS8737 0x00221720
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#define PHY_ID_KSZ8021 0x00221555
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#define PHY_ID_KSZ8031 0x00221556
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#define PHY_ID_KSZ8041 0x00221510
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/* undocumented */
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#define PHY_ID_KSZ8041RNLI 0x00221537
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#define PHY_ID_KSZ8051 0x00221550
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/* same id: ks8001 Rev. A/B, and ks8721 Rev 3. */
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#define PHY_ID_KSZ8001 0x0022161A
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/* same id: KS8081, KS8091 */
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#define PHY_ID_KSZ8081 0x00221560
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#define PHY_ID_KSZ8061 0x00221570
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#define PHY_ID_KSZ9031 0x00221620
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#define PHY_ID_KSZ9131 0x00221640
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#define PHY_ID_LAN8814 0x00221660
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#define PHY_ID_KSZ886X 0x00221430
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#define PHY_ID_KSZ8863 0x00221435
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#define PHY_ID_KSZ87XX 0x00221550
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#define PHY_ID_KSZ9477 0x00221631
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/* struct phy_device dev_flags definitions */
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#define MICREL_PHY_50MHZ_CLK 0x00000001
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#define MICREL_PHY_FXEN 0x00000002
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#define MICREL_KSZ9021_EXTREG_CTRL 0xB
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#define MICREL_KSZ9021_EXTREG_DATA_WRITE 0xC
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#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
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#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW 0x105
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#endif /* _MICREL_PHY_H */
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