352 lines
9.9 KiB
Plaintext
352 lines
9.9 KiB
Plaintext
Freescale i.MX DRM master device
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================================
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The freescale i.MX DRM master device is a virtual device needed to list all
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IPU or other display interface nodes that comprise the graphics subsystem.
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Required properties:
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- compatible: Should be "fsl,imx-display-subsystem"
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- ports: Should contain a list of phandles pointing to display interface ports
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of IPU devices
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example:
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display-subsystem {
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compatible = "fsl,display-subsystem";
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ports = <&ipu_di0>;
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};
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Freescale i.MX IPUv3
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====================
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Required properties:
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- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
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- imx51
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- imx53
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- imx6q
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- imx6qp
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain sync interrupt and error interrupt,
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in this order.
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- resets: phandle pointing to the system reset controller and
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reset line index, see reset/fsl,imx-src.txt for details
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Additional required properties for fsl,imx6qp-ipu:
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- fsl,prg: phandle to prg node associated with this IPU instance
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Optional properties:
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- port@[0-3]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Ports 0 and 1 should correspond to CSI0 and CSI1,
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ports 2 and 3 should correspond to DI0 and DI1, respectively.
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example:
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ipu: ipu@18000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x080000000>;
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interrupts = <11 10>;
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resets = <&src 2>;
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ipu_di0: port@2 {
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reg = <2>;
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ipu_di0_disp0: endpoint {
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remote-endpoint = <&display_in>;
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};
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};
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};
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Freescale i.MX PRE (Prefetch Resolve Engine)
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============================================
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Required properties:
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- compatible: should be "fsl,imx6qp-pre"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks : phandle to the PRE axi clock input, as described
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in Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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- clock-names: should be "axi"
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- interrupts: should contain the PRE interrupt
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- fsl,iram: phandle pointing to the mmio-sram device node, that should be
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used for the PRE SRAM double buffer.
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example:
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pre@21c8000 {
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compatible = "fsl,imx6qp-pre";
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reg = <0x021c8000 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clks IMX6QDL_CLK_PRE0>;
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clock-names = "axi";
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fsl,iram = <&ocram2>;
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};
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Freescale i.MX PRG (Prefetch Resolve Gasket)
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============================================
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Required properties:
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- compatible: should be "fsl,imx6qp-prg"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks : phandles to the PRG ipg and axi clock inputs, as described
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in Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx6q-clock.txt.
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- clock-names: should be "ipg" and "axi"
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- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
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PRE as the first entry and the muxable PREs following.
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example:
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prg@21cc000 {
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compatible = "fsl,imx6qp-prg";
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reg = <0x021cc000 0x1000>;
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clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
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<&clks IMX6QDL_CLK_PRG0_AXI>;
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clock-names = "ipg", "axi";
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fsl,pres = <&pre1>, <&pre2>, <&pre3>;
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};
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Freescale i.MX DPU
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====================
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Required properties:
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- compatible: Should be "fsl,<chip>-dpu"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupt-parent: phandle pointing to the parent interrupt controller.
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- interrupts, interrupt-names: Should contain interrupts and names as
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documented in the datasheet.
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- clocks, clock-names: phandles to the DPU clocks described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The following clocks are expected on i.MX8qxp:
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"pll0" - PLL clock for display interface 0
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"pll1" - PLL clock for display interface 1
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"disp0" - pixel clock for display interface 0
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"disp1" - pixel clock for display interface 1
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The needed clock numbers for each are documented in
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Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
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- power-domains: phandles pointing to power domain.
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- power-domain-names: power domain names relevant to power-domains phandles.
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Optional properties:
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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ports 0 and 1 should correspond to display interface 0 and
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display interface 1, respectively.
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example:
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dpu: dpu@56180000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qxp-dpu";
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reg = <0x56180000 0x40000>;
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interrupt-parent = <&irqsteer_dpu>;
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interrupts = <448>, <449>, <450>, <64>,
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<65>, <66>, <67>, <68>,
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<69>, <70>, <193>, <194>,
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<195>, <196>, <197>, <72>,
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<73>, <74>, <75>, <76>,
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<77>, <78>, <79>, <80>,
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<81>, <199>, <200>, <201>,
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<202>, <203>, <204>, <205>,
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<206>, <207>, <208>, <0>,
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<1>, <2>, <3>, <4>,
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<82>, <83>, <84>, <85>,
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<209>, <210>, <211>, <212>;
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interrupt-names = "store9_shdload",
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"store9_framecomplete",
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"store9_seqcomplete",
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"extdst0_shdload",
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"extdst0_framecomplete",
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"extdst0_seqcomplete",
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"extdst4_shdload",
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"extdst4_framecomplete",
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"extdst4_seqcomplete",
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"extdst1_shdload",
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"extdst1_framecomplete",
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"extdst1_seqcomplete",
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"extdst5_shdload",
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"extdst5_framecomplete",
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"extdst5_seqcomplete",
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"disengcfg_shdload0",
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"disengcfg_framecomplete0",
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"disengcfg_seqcomplete0",
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"framegen0_int0",
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"framegen0_int1",
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"framegen0_int2",
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"framegen0_int3",
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"sig0_shdload",
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"sig0_valid",
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"sig0_error",
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"disengcfg_shdload1",
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"disengcfg_framecomplete1",
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"disengcfg_seqcomplete1",
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"framegen1_int0",
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"framegen1_int1",
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"framegen1_int2",
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"framegen1_int3",
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"sig1_shdload",
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"sig1_valid",
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"sig1_error",
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"cmdseq_error",
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"comctrl_sw0",
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"comctrl_sw1",
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"comctrl_sw2",
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"comctrl_sw3",
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"framegen0_primsync_on",
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"framegen0_primsync_off",
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"framegen0_secsync_on",
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"framegen0_secsync_off",
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"framegen1_primsync_on",
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"framegen1_primsync_off",
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"framegen1_secsync_on",
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"framegen1_secsync_off";
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clocks = <&dc_lpcg IMX_DC0_PLL0_CLK>,
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<&dc_lpcg IMX_DC0_PLL1_CLK>,
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<&dc_lpcg IMX_DC0_DISP0_CLK>,
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<&dc_lpcg IMX_DC0_DISP1_CLK>;
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clock-names = "pll0", "pll1", "disp0", "disp1";
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power-domains = <&pd IMX_SC_R_DC_0>,
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<&pd IMX_SC_R_DC_0_PLL_0>,
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<&pd IMX_SC_R_DC_0_PLL_1>;
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power-domain-names = "dc", "pll0", "pll1";
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dpu_disp0: port@0 {
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reg = <0>;
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dpu_disp0_lvds0_ch0: endpoint@0 {
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remote-endpoint = <&ldb1_ch0>;
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};
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dpu_disp0_lvds0_ch1: endpoint@1 {
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remote-endpoint = <&ldb1_ch1>;
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};
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dpu_disp0_mipi_dsi: endpoint@2 {
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};
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};
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dpu_disp1: port@1 {
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reg = <1>;
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dpu_disp1_lvds1_ch0: endpoint@0 {
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remote-endpoint = <&ldb2_ch0>;
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};
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dpu_disp1_lvds1_ch1: endpoint@1 {
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remote-endpoint = <&ldb2_ch1>;
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};
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dpu_disp1_mipi_dsi: endpoint@2 {
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};
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};
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};
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Freescale i.MX8 PRG (Prefetch Resolve Gasket)
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=============================================
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Required properties:
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- compatible: should be "fsl,<chip>-prg"
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- reg: should be register base and length as documented in the
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datasheet
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- clocks: phandles to the PRG apb and rtram clocks, as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
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- clock-names: should be "apb" and "rtram"
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- power-domains: phandle pointing to power domain
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example:
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prg@56040000 {
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compatible = "fsl,imx8qm-prg";
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reg = <0x56040000 0x10000>;
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clocks = <&dc0_prg0_lpcg 0>, <&dc0_prg0_lpcg 1>;
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clock-names = "apb", "rtram";
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power-domains = <&pd IMX_SC_R_DC_0>;
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};
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Freescale i.MX8 DPRC (Display Prefetch Resolve Channel)
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=======================================================
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Required properties:
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- compatible: should be "fsl,<chip>-dpr-channel"
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- reg: should be register base and length as documented in the
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datasheet
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- fsl,sc-resource: SCU resource number as defined in
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include/dt-bindings/firmware/imx/rsrc.h
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- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one
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is the primary PRG and the second one(if available) is the auxiliary PRG
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which is used to fetch luma chunk of a YUV frame with 2 planars.
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- clocks: phandles to the DPRC apb, b and rtram clocks, as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt and
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Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt.
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- clock-names: should be "apb", "b" and "rtram"
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- power-domains: phandle pointing to power domain
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example:
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dpr-channel@560e0000 {
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compatible = "fsl,imx8qm-dpr-channel";
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reg = <0x560e0000 0x10000>;
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fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
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fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
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clocks = <&dc0_dpr0_lpcg 0>,
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<&dc0_dpr0_lpcg 1>,
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<&dc0_rtram0_lpcg 0>;
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clock-names = "apb", "b", "rtram";
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power-domains = <&pd IMX_SC_R_DC_0>;
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};
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Parallel display support
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========================
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Required properties:
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- compatible: Should be "fsl,imx-parallel-display"
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Optional properties:
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- interface-pix-fmt: How this display is connected to the
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display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
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and "lvds666".
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- edid: verbatim EDID data block describing attached display.
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- ddc: phandle describing the i2c bus handling the display data
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channel
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- port@[0-1]: Port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Port 0 is the input port connected to the IPU display interface,
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port 1 is the output port connected to a panel.
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example:
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disp0 {
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compatible = "fsl,imx-parallel-display";
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edid = [edid-data];
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interface-pix-fmt = "rgb24";
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port@0 {
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reg = <0>;
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display_in: endpoint {
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remote-endpoint = <&ipu_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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panel {
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...
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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