![Thomas Gleixner](/assets/img/avatar_default.png)
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
819 lines
22 KiB
C
819 lines
22 KiB
C
/*
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* OMAP2+ common Power & Reset Management (PRM) IP block functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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* For historical purposes, the API used to configure the PRM
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* interrupt handler refers to it as the "PRCM interrupt." The
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* underlying registers are located in the PRM on OMAP3/4.
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*
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* XXX This code should eventually be moved to a PRM driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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#include "soc.h"
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#include "prm2xxx_3xxx.h"
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#include "prm2xxx.h"
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#include "prm3xxx.h"
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#include "prm33xx.h"
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#include "prm44xx.h"
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#include "prm54xx.h"
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#include "prm7xx.h"
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#include "prcm43xx.h"
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#include "common.h"
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#include "clock.h"
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#include "cm.h"
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#include "control.h"
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/*
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* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
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* XXX this is technically not needed, since
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* omap_prcm_register_chain_handler() could allocate this based on the
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* actual amount of memory needed for the SoC
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*/
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#define OMAP_PRCM_MAX_NR_PENDING_REG 2
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/*
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* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
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* by the PRCM interrupt handler code. There will be one 'chip' per
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* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
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* one "chip" and OMAP4 will have two.)
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*/
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static struct irq_chip_generic **prcm_irq_chips;
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/*
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* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
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* is currently running on. Defined and passed by initialization code
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* that calls omap_prcm_register_chain_handler().
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*/
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static struct omap_prcm_irq_setup *prcm_irq_setup;
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/* prm_base: base virtual address of the PRM IP block */
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void __iomem *prm_base;
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u16 prm_features;
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/*
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* prm_ll_data: function pointers to SoC-specific implementations of
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* common PRM functions
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*/
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static struct prm_ll_data null_prm_ll_data;
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static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
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/* Private functions */
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/*
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* Move priority events from events to priority_events array
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*/
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static void omap_prcm_events_filter_priority(unsigned long *events,
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unsigned long *priority_events)
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{
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int i;
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for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
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priority_events[i] =
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events[i] & prcm_irq_setup->priority_mask[i];
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events[i] ^= priority_events[i];
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}
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}
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/*
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* PRCM Interrupt Handler
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*
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* This is a common handler for the OMAP PRCM interrupts. Pending
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* interrupts are detected by a call to prcm_pending_events and
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* dispatched accordingly. Clearing of the wakeup events should be
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* done by the SoC specific individual handlers.
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*/
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static void omap_prcm_irq_handler(struct irq_desc *desc)
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{
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unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
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unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int virtirq;
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int nr_irq = prcm_irq_setup->nr_regs * 32;
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/*
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* If we are suspended, mask all interrupts from PRCM level,
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* this does not ack them, and they will be pending until we
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* re-enable the interrupts, at which point the
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* omap_prcm_irq_handler will be executed again. The
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* _save_and_clear_irqen() function must ensure that the PRM
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* write to disable all IRQs has reached the PRM before
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* returning, or spurious PRCM interrupts may occur during
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* suspend.
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*/
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if (prcm_irq_setup->suspended) {
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prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
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prcm_irq_setup->suspend_save_flag = true;
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}
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/*
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* Loop until all pending irqs are handled, since
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* generic_handle_irq() can cause new irqs to come
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*/
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while (!prcm_irq_setup->suspended) {
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prcm_irq_setup->read_pending_irqs(pending);
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/* No bit set, then all IRQs are handled */
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if (find_first_bit(pending, nr_irq) >= nr_irq)
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break;
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omap_prcm_events_filter_priority(pending, priority_pending);
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/*
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* Loop on all currently pending irqs so that new irqs
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* cannot starve previously pending irqs
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*/
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/* Serve priority events first */
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for_each_set_bit(virtirq, priority_pending, nr_irq)
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generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
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/* Serve normal events next */
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for_each_set_bit(virtirq, pending, nr_irq)
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generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
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}
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if (chip->irq_ack)
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chip->irq_ack(&desc->irq_data);
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if (chip->irq_eoi)
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chip->irq_eoi(&desc->irq_data);
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chip->irq_unmask(&desc->irq_data);
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prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
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}
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/* Public functions */
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/**
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* omap_prcm_event_to_irq - given a PRCM event name, returns the
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* corresponding IRQ on which the handler should be registered
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* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
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*
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* Returns the Linux internal IRQ ID corresponding to @name upon success,
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* or -ENOENT upon failure.
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*/
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int omap_prcm_event_to_irq(const char *name)
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{
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int i;
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if (!prcm_irq_setup || !name)
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return -ENOENT;
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for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
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if (!strcmp(prcm_irq_setup->irqs[i].name, name))
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return prcm_irq_setup->base_irq +
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prcm_irq_setup->irqs[i].offset;
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return -ENOENT;
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}
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/**
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* omap_prcm_irq_cleanup - reverses memory allocated and other steps
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* done by omap_prcm_register_chain_handler()
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*
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* No return value.
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*/
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void omap_prcm_irq_cleanup(void)
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{
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unsigned int irq;
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int i;
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if (!prcm_irq_setup) {
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pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
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return;
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}
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if (prcm_irq_chips) {
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for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
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if (prcm_irq_chips[i])
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irq_remove_generic_chip(prcm_irq_chips[i],
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0xffffffff, 0, 0);
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prcm_irq_chips[i] = NULL;
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}
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kfree(prcm_irq_chips);
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prcm_irq_chips = NULL;
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}
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kfree(prcm_irq_setup->saved_mask);
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prcm_irq_setup->saved_mask = NULL;
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kfree(prcm_irq_setup->priority_mask);
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prcm_irq_setup->priority_mask = NULL;
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if (prcm_irq_setup->xlate_irq)
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irq = prcm_irq_setup->xlate_irq(prcm_irq_setup->irq);
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else
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irq = prcm_irq_setup->irq;
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irq_set_chained_handler(irq, NULL);
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if (prcm_irq_setup->base_irq > 0)
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irq_free_descs(prcm_irq_setup->base_irq,
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prcm_irq_setup->nr_regs * 32);
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prcm_irq_setup->base_irq = 0;
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}
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void omap_prcm_irq_prepare(void)
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{
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prcm_irq_setup->suspended = true;
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}
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void omap_prcm_irq_complete(void)
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{
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prcm_irq_setup->suspended = false;
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/* If we have not saved the masks, do not attempt to restore */
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if (!prcm_irq_setup->suspend_save_flag)
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return;
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prcm_irq_setup->suspend_save_flag = false;
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/*
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* Re-enable all masked PRCM irq sources, this causes the PRCM
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* interrupt to fire immediately if the events were masked
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* previously in the chain handler
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*/
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prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
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}
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/**
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* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
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* handler based on provided parameters
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* @irq_setup: hardware data about the underlying PRM/PRCM
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*
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* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
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* one generic IRQ chip per PRM interrupt status/enable register pair.
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* Returns 0 upon success, -EINVAL if called twice or if invalid
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* arguments are passed, or -ENOMEM on any other error.
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*/
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int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
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{
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int nr_regs;
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u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
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int offset, i;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int irq;
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if (!irq_setup)
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return -EINVAL;
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nr_regs = irq_setup->nr_regs;
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if (prcm_irq_setup) {
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pr_err("PRCM: already initialized; won't reinitialize\n");
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return -EINVAL;
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}
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if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
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pr_err("PRCM: nr_regs too large\n");
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return -EINVAL;
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}
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prcm_irq_setup = irq_setup;
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prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
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prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
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prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
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GFP_KERNEL);
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if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
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!prcm_irq_setup->priority_mask) {
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pr_err("PRCM: kzalloc failed\n");
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goto err;
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}
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memset(mask, 0, sizeof(mask));
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for (i = 0; i < irq_setup->nr_irqs; i++) {
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offset = irq_setup->irqs[i].offset;
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mask[offset >> 5] |= 1 << (offset & 0x1f);
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if (irq_setup->irqs[i].priority)
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irq_setup->priority_mask[offset >> 5] |=
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1 << (offset & 0x1f);
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}
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if (irq_setup->xlate_irq)
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irq = irq_setup->xlate_irq(irq_setup->irq);
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else
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irq = irq_setup->irq;
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irq_set_chained_handler(irq, omap_prcm_irq_handler);
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irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
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0);
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if (irq_setup->base_irq < 0) {
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pr_err("PRCM: failed to allocate irq descs: %d\n",
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irq_setup->base_irq);
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goto err;
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}
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for (i = 0; i < irq_setup->nr_regs; i++) {
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gc = irq_alloc_generic_chip("PRCM", 1,
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irq_setup->base_irq + i * 32, prm_base,
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handle_level_irq);
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if (!gc) {
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pr_err("PRCM: failed to allocate generic chip\n");
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goto err;
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}
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.ack = irq_setup->ack + i * 4;
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ct->regs.mask = irq_setup->mask + i * 4;
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irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
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prcm_irq_chips[i] = gc;
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}
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if (of_have_populated_dt()) {
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int irq = omap_prcm_event_to_irq("io");
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omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
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}
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return 0;
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err:
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omap_prcm_irq_cleanup();
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return -ENOMEM;
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}
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/**
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* omap2_set_globals_prm - set the PRM base address (for early use)
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* @prm: PRM base virtual address
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*
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* XXX Will be replaced when the PRM/CM drivers are completed.
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*/
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void __init omap2_set_globals_prm(void __iomem *prm)
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{
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prm_base = prm;
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}
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/**
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* prm_read_reset_sources - return the sources of the SoC's last reset
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*
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* Return a u32 bitmask representing the reset sources that caused the
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* SoC to reset. The low-level per-SoC functions called by this
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* function remap the SoC-specific reset source bits into an
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* OMAP-common set of reset source bits, defined in
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* arch/arm/mach-omap2/prm.h. Returns the standardized reset source
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* u32 bitmask from the hardware upon success, or returns (1 <<
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* OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
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* function was registered.
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*/
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u32 prm_read_reset_sources(void)
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{
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u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
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if (prm_ll_data->read_reset_sources)
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ret = prm_ll_data->read_reset_sources();
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else
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WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
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return ret;
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}
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/**
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* prm_was_any_context_lost_old - was device context lost? (old API)
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* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
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* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
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* @idx: CONTEXT register offset
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*
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* Return 1 if any bits were set in the *_CONTEXT_* register
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* identified by (@part, @inst, @idx), which means that some context
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* was lost for that module; otherwise, return 0. XXX Deprecated;
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* callers need to use a less-SoC-dependent way to identify hardware
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* IP blocks.
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*/
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bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
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{
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bool ret = true;
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if (prm_ll_data->was_any_context_lost_old)
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ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
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else
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WARN_ONCE(1, "prm: %s: no mapping function defined\n",
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__func__);
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return ret;
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}
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/**
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* prm_clear_context_lost_flags_old - clear context loss flags (old API)
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* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
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* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
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* @idx: CONTEXT register offset
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*
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* Clear hardware context loss bits for the module identified by
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* (@part, @inst, @idx). No return value. XXX Deprecated; callers
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* need to use a less-SoC-dependent way to identify hardware IP
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* blocks.
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*/
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void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
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{
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if (prm_ll_data->clear_context_loss_flags_old)
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prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
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else
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WARN_ONCE(1, "prm: %s: no mapping function defined\n",
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__func__);
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}
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/**
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* omap_prm_assert_hardreset - assert hardreset for an IP block
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* @shift: register bit shift corresponding to the reset line
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* @part: PRM partition
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* @prm_mod: PRM submodule base or instance offset
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* @offset: register offset
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*
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* Asserts a hardware reset line for an IP block.
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*/
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int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset)
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{
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if (!prm_ll_data->assert_hardreset) {
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WARN_ONCE(1, "prm: %s: no mapping function defined\n",
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__func__);
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return -EINVAL;
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}
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return prm_ll_data->assert_hardreset(shift, part, prm_mod, offset);
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}
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/**
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* omap_prm_deassert_hardreset - deassert hardreset for an IP block
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* @shift: register bit shift corresponding to the reset line
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* @st_shift: reset status bit shift corresponding to the reset line
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* @part: PRM partition
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* @prm_mod: PRM submodule base or instance offset
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* @offset: register offset
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* @st_offset: status register offset
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*
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* Deasserts a hardware reset line for an IP block.
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*/
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int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
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u16 offset, u16 st_offset)
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{
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if (!prm_ll_data->deassert_hardreset) {
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WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return prm_ll_data->deassert_hardreset(shift, st_shift, part, prm_mod,
|
|
offset, st_offset);
|
|
}
|
|
|
|
/**
|
|
* omap_prm_is_hardreset_asserted - check the hardreset status for an IP block
|
|
* @shift: register bit shift corresponding to the reset line
|
|
* @part: PRM partition
|
|
* @prm_mod: PRM submodule base or instance offset
|
|
* @offset: register offset
|
|
*
|
|
* Checks if a hardware reset line for an IP block is enabled or not.
|
|
*/
|
|
int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset)
|
|
{
|
|
if (!prm_ll_data->is_hardreset_asserted) {
|
|
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return prm_ll_data->is_hardreset_asserted(shift, part, prm_mod, offset);
|
|
}
|
|
|
|
/**
|
|
* omap_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
|
|
*
|
|
* Clear any previously-latched I/O wakeup events and ensure that the
|
|
* I/O wakeup gates are aligned with the current mux settings.
|
|
* Calls SoC specific I/O chain reconfigure function if available,
|
|
* otherwise does nothing.
|
|
*/
|
|
void omap_prm_reconfigure_io_chain(void)
|
|
{
|
|
if (!prcm_irq_setup || !prcm_irq_setup->reconfigure_io_chain)
|
|
return;
|
|
|
|
prcm_irq_setup->reconfigure_io_chain();
|
|
}
|
|
|
|
/**
|
|
* omap_prm_reset_system - trigger global SW reset
|
|
*
|
|
* Triggers SoC specific global warm reset to reboot the device.
|
|
*/
|
|
void omap_prm_reset_system(void)
|
|
{
|
|
if (!prm_ll_data->reset_system) {
|
|
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return;
|
|
}
|
|
|
|
prm_ll_data->reset_system();
|
|
|
|
while (1)
|
|
cpu_relax();
|
|
}
|
|
|
|
/**
|
|
* omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
|
|
* @module: PRM module to clear wakeups from
|
|
* @regs: register to clear
|
|
* @wkst_mask: wkst bits to clear
|
|
*
|
|
* Clears any wakeup events for the module and register set defined.
|
|
* Uses SoC specific implementation to do the actual wakeup status
|
|
* clearing.
|
|
*/
|
|
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
|
|
{
|
|
if (!prm_ll_data->clear_mod_irqs) {
|
|
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
|
|
}
|
|
|
|
/**
|
|
* omap_prm_vp_check_txdone - check voltage processor TX done status
|
|
*
|
|
* Checks if voltage processor transmission has been completed.
|
|
* Returns non-zero if a transmission has completed, 0 otherwise.
|
|
*/
|
|
u32 omap_prm_vp_check_txdone(u8 vp_id)
|
|
{
|
|
if (!prm_ll_data->vp_check_txdone) {
|
|
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return 0;
|
|
}
|
|
|
|
return prm_ll_data->vp_check_txdone(vp_id);
|
|
}
|
|
|
|
/**
|
|
* omap_prm_vp_clear_txdone - clears voltage processor TX done status
|
|
*
|
|
* Clears the status bit for completed voltage processor transmission
|
|
* returned by prm_vp_check_txdone.
|
|
*/
|
|
void omap_prm_vp_clear_txdone(u8 vp_id)
|
|
{
|
|
if (!prm_ll_data->vp_clear_txdone) {
|
|
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
|
|
__func__);
|
|
return;
|
|
}
|
|
|
|
prm_ll_data->vp_clear_txdone(vp_id);
|
|
}
|
|
|
|
/**
|
|
* prm_register - register per-SoC low-level data with the PRM
|
|
* @pld: low-level per-SoC OMAP PRM data & function pointers to register
|
|
*
|
|
* Register per-SoC low-level OMAP PRM data and function pointers with
|
|
* the OMAP PRM common interface. The caller must keep the data
|
|
* pointed to by @pld valid until it calls prm_unregister() and
|
|
* it returns successfully. Returns 0 upon success, -EINVAL if @pld
|
|
* is NULL, or -EEXIST if prm_register() has already been called
|
|
* without an intervening prm_unregister().
|
|
*/
|
|
int prm_register(struct prm_ll_data *pld)
|
|
{
|
|
if (!pld)
|
|
return -EINVAL;
|
|
|
|
if (prm_ll_data != &null_prm_ll_data)
|
|
return -EEXIST;
|
|
|
|
prm_ll_data = pld;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* prm_unregister - unregister per-SoC low-level data & function pointers
|
|
* @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
|
|
*
|
|
* Unregister per-SoC low-level OMAP PRM data and function pointers
|
|
* that were previously registered with prm_register(). The
|
|
* caller may not destroy any of the data pointed to by @pld until
|
|
* this function returns successfully. Returns 0 upon success, or
|
|
* -EINVAL if @pld is NULL or if @pld does not match the struct
|
|
* prm_ll_data * previously registered by prm_register().
|
|
*/
|
|
int prm_unregister(struct prm_ll_data *pld)
|
|
{
|
|
if (!pld || prm_ll_data != pld)
|
|
return -EINVAL;
|
|
|
|
prm_ll_data = &null_prm_ll_data;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
static struct omap_prcm_init_data omap2_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap2xxx_prm_init,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct omap_prcm_init_data omap3_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap3xxx_prm_init,
|
|
|
|
/*
|
|
* IVA2 offset is a negative value, must offset the prm_base
|
|
* address by this to get it to positive
|
|
*/
|
|
.offset = -OMAP3430_IVA2_MOD,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
|
|
static struct omap_prcm_init_data am3_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = am33xx_prm_init,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
static struct omap_prcm_init_data omap4_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap44xx_prm_init,
|
|
.device_inst_offset = OMAP4430_PRM_DEVICE_INST,
|
|
.flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
static struct omap_prcm_init_data omap5_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap44xx_prm_init,
|
|
.device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
|
|
.flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_DRA7XX
|
|
static struct omap_prcm_init_data dra7_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap44xx_prm_init,
|
|
.device_inst_offset = DRA7XX_PRM_DEVICE_INST,
|
|
.flags = PRM_HAS_IO_WAKEUP,
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_AM43XX
|
|
static struct omap_prcm_init_data am4_prm_data __initdata = {
|
|
.index = TI_CLKM_PRM,
|
|
.init = omap44xx_prm_init,
|
|
.device_inst_offset = AM43XX_PRM_DEVICE_INST,
|
|
.flags = PRM_HAS_IO_WAKEUP,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
|
|
static struct omap_prcm_init_data scrm_data __initdata = {
|
|
.index = TI_CLKM_SCRM,
|
|
};
|
|
#endif
|
|
|
|
static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = {
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
{ .compatible = "ti,am3-prcm", .data = &am3_prm_data },
|
|
#endif
|
|
#ifdef CONFIG_SOC_AM43XX
|
|
{ .compatible = "ti,am4-prcm", .data = &am4_prm_data },
|
|
#endif
|
|
#ifdef CONFIG_SOC_TI81XX
|
|
{ .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
|
|
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
{ .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
|
|
#endif
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
{ .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
|
|
{ .compatible = "ti,omap4-scrm", .data = &scrm_data },
|
|
#endif
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
{ .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
|
|
{ .compatible = "ti,omap5-scrm", .data = &scrm_data },
|
|
#endif
|
|
#ifdef CONFIG_SOC_DRA7XX
|
|
{ .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
|
|
#endif
|
|
{ }
|
|
};
|
|
|
|
/**
|
|
* omap2_prm_base_init - initialize iomappings for the PRM driver
|
|
*
|
|
* Detects and initializes the iomappings for the PRM driver, based
|
|
* on the DT data. Returns 0 in success, negative error value
|
|
* otherwise.
|
|
*/
|
|
int __init omap2_prm_base_init(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *match;
|
|
struct omap_prcm_init_data *data;
|
|
void __iomem *mem;
|
|
|
|
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
|
|
data = (struct omap_prcm_init_data *)match->data;
|
|
|
|
mem = of_iomap(np, 0);
|
|
if (!mem)
|
|
return -ENOMEM;
|
|
|
|
if (data->index == TI_CLKM_PRM)
|
|
prm_base = mem + data->offset;
|
|
|
|
data->mem = mem;
|
|
|
|
data->np = np;
|
|
|
|
if (data->init)
|
|
data->init(data);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init omap2_prcm_base_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = omap2_prm_base_init();
|
|
if (ret)
|
|
return ret;
|
|
|
|
return omap2_cm_base_init();
|
|
}
|
|
|
|
/**
|
|
* omap_prcm_init - low level init for the PRCM drivers
|
|
*
|
|
* Initializes the low level clock infrastructure for PRCM drivers.
|
|
* Returns 0 in success, negative error value in failure.
|
|
*/
|
|
int __init omap_prcm_init(void)
|
|
{
|
|
struct device_node *np;
|
|
const struct of_device_id *match;
|
|
const struct omap_prcm_init_data *data;
|
|
int ret;
|
|
|
|
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
|
|
data = match->data;
|
|
|
|
ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
omap_cm_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init prm_late_init(void)
|
|
{
|
|
if (prm_ll_data->late_init)
|
|
return prm_ll_data->late_init();
|
|
return 0;
|
|
}
|
|
subsys_initcall(prm_late_init);
|