![Caesar Wang](/assets/img/avatar_default.png)
The following was seen in branch[0] build. arch/arm/mach-rockchip/platsmp.c:154:23: error: 'rockchip_secondary_startup' undeclared (first use in this function) branch[0]: git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git v4.3-armsoc/soc The broken build is caused by the commitfe4407c0dc
("ARM: rockchip: fix the CPU soft reset"). Signed-off-by: Caesar Wang <wxt@rock-chips.com> The breakage was a result of it being wrongly merged in my branch with the cache invalidation rework from Russell02b4e2756e
("ARM: v7 setup function should invalidate L1 cache"). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
353 lines
8.6 KiB
C
353 lines
8.6 KiB
C
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/reset.h>
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/map.h>
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#include "core.h"
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static void __iomem *scu_base_addr;
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static void __iomem *sram_base_addr;
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static int ncores;
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#define PMU_PWRDN_CON 0x08
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#define PMU_PWRDN_ST 0x0c
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#define PMU_PWRDN_SCU 4
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static struct regmap *pmu;
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static int pmu_power_domain_is_on(int pd)
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{
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u32 val;
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int ret;
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ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
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if (ret < 0)
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return ret;
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return !(val & BIT(pd));
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}
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static struct reset_control *rockchip_get_core_reset(int cpu)
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{
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struct device *dev = get_cpu_device(cpu);
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struct device_node *np;
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/* The cpu device is only available after the initial core bringup */
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if (dev)
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np = dev->of_node;
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else
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np = of_get_cpu_node(cpu, 0);
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return of_reset_control_get(np, NULL);
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}
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static int pmu_set_power_domain(int pd, bool on)
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{
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u32 val = (on) ? 0 : BIT(pd);
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struct reset_control *rstc = rockchip_get_core_reset(pd);
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int ret;
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if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
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pr_err("%s: could not get reset control for core %d\n",
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__func__, pd);
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return PTR_ERR(rstc);
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}
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/*
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* We need to soft reset the cpu when we turn off the cpu power domain,
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* or else the active processors might be stalled when the individual
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* processor is powered down.
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*/
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if (!IS_ERR(rstc) && !on)
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reset_control_assert(rstc);
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ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
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if (ret < 0) {
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pr_err("%s: could not update power domain\n", __func__);
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return ret;
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}
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ret = -1;
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while (ret != on) {
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ret = pmu_power_domain_is_on(pd);
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if (ret < 0) {
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pr_err("%s: could not read power domain state\n",
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__func__);
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return ret;
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}
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}
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if (!IS_ERR(rstc)) {
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if (on)
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reset_control_deassert(rstc);
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reset_control_put(rstc);
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}
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return 0;
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}
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/*
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* Handling of CPU cores
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*/
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static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int ret;
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if (!sram_base_addr || !pmu) {
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pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
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return -ENXIO;
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}
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if (cpu >= ncores) {
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pr_err("%s: cpu %d outside maximum number of cpus %d\n",
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__func__, cpu, ncores);
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return -ENXIO;
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}
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/* start the core */
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ret = pmu_set_power_domain(0 + cpu, true);
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if (ret < 0)
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return ret;
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if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
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/*
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* We communicate with the bootrom to active the cpus other
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* than cpu0, after a blob of initialize code, they will
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* stay at wfe state, once they are actived, they will check
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* the mailbox:
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* sram_base_addr + 4: 0xdeadbeaf
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* sram_base_addr + 8: start address for pc
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* The cpu0 need to wait the other cpus other than cpu0 entering
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* the wfe state.The wait time is affected by many aspects.
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* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
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*/
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mdelay(1); /* ensure the cpus other than cpu0 to startup */
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writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
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writel(0xDEADBEAF, sram_base_addr + 4);
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dsb_sev();
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}
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return 0;
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}
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/**
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* rockchip_smp_prepare_sram - populate necessary sram block
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* Starting cores execute the code residing at the start of the on-chip sram
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* after power-on. Therefore make sure, this sram region is reserved and
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* big enough. After this check, copy the trampoline code that directs the
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* core to the real startup code in ram into the sram-region.
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* @node: mmio-sram device node
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*/
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static int __init rockchip_smp_prepare_sram(struct device_node *node)
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{
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unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
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&rockchip_secondary_trampoline;
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struct resource res;
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unsigned int rsize;
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int ret;
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ret = of_address_to_resource(node, 0, &res);
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if (ret < 0) {
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pr_err("%s: could not get address for node %s\n",
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__func__, node->full_name);
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return ret;
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}
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rsize = resource_size(&res);
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if (rsize < trampoline_sz) {
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pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
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__func__, rsize, trampoline_sz);
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return -EINVAL;
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}
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/* set the boot function for the sram code */
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rockchip_boot_fn = virt_to_phys(secondary_startup);
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/* copy the trampoline to sram, that runs during startup of the core */
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memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
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flush_cache_all();
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outer_clean_range(0, trampoline_sz);
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dsb_sev();
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return 0;
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}
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static const struct regmap_config rockchip_pmu_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int __init rockchip_smp_prepare_pmu(void)
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{
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struct device_node *node;
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void __iomem *pmu_base;
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/*
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* This function is only called via smp_ops->smp_prepare_cpu().
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* That only happens if a "/cpus" device tree node exists
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* and has an "enable-method" property that selects the SMP
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* operations defined herein.
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*/
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node = of_find_node_by_path("/cpus");
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pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
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of_node_put(node);
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if (!IS_ERR(pmu))
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return 0;
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pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
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if (!IS_ERR(pmu))
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return 0;
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/* fallback, create our own regmap for the pmu area */
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pmu = NULL;
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node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
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if (!node) {
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pr_err("%s: could not find pmu dt node\n", __func__);
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return -ENODEV;
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}
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pmu_base = of_iomap(node, 0);
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if (!pmu_base) {
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pr_err("%s: could not map pmu registers\n", __func__);
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return -ENOMEM;
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}
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pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
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if (IS_ERR(pmu)) {
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int ret = PTR_ERR(pmu);
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iounmap(pmu_base);
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pmu = NULL;
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pr_err("%s: regmap init failed\n", __func__);
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return ret;
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}
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return 0;
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}
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static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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unsigned int i;
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node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
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if (!node) {
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pr_err("%s: could not find sram dt node\n", __func__);
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return;
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}
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sram_base_addr = of_iomap(node, 0);
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if (!sram_base_addr) {
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pr_err("%s: could not map sram registers\n", __func__);
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return;
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}
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if (rockchip_smp_prepare_pmu())
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return;
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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if (rockchip_smp_prepare_sram(node))
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return;
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/* enable the SCU power domain */
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pmu_set_power_domain(PMU_PWRDN_SCU, true);
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!node) {
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pr_err("%s: missing scu\n", __func__);
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return;
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}
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scu_base_addr = of_iomap(node, 0);
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if (!scu_base_addr) {
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pr_err("%s: could not map scu registers\n", __func__);
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return;
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}
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/*
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* While the number of cpus is gathered from dt, also get the
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* number of cores from the scu to verify this value when
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* booting the cores.
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*/
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ncores = scu_get_core_count(scu_base_addr);
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pr_err("%s: ncores %d\n", __func__, ncores);
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scu_enable(scu_base_addr);
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} else {
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unsigned int l2ctlr;
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asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
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ncores = ((l2ctlr >> 24) & 0x3) + 1;
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}
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/* Make sure that all cores except the first are really off */
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for (i = 1; i < ncores; i++)
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pmu_set_power_domain(0 + i, false);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int rockchip_cpu_kill(unsigned int cpu)
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{
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/*
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* We need a delay here to ensure that the dying CPU can finish
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* executing v7_coherency_exit() and reach the WFI/WFE state
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* prior to having the power domain disabled.
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*/
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mdelay(1);
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pmu_set_power_domain(0 + cpu, false);
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return 1;
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}
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static void rockchip_cpu_die(unsigned int cpu)
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{
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v7_exit_coherency_flush(louis);
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while (1)
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cpu_do_idle();
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}
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#endif
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static struct smp_operations rockchip_smp_ops __initdata = {
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.smp_prepare_cpus = rockchip_smp_prepare_cpus,
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.smp_boot_secondary = rockchip_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = rockchip_cpu_kill,
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.cpu_die = rockchip_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
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