c00def71ef
This removes a lot of ancient cruft from the Ux500 SMP boot. Instead of the pen grab/release, just point the ROM to secondary_boot() and start the second CPU there, then send the IPI. Use our own SMP enable method. This enables us to remove the last static mapping and get both CPUs booting properly. Tested this and it just works. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
109 lines
2.6 KiB
C
109 lines
2.6 KiB
C
/*
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* Copyright (C) 2002 ARM Ltd.
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* Copyright (C) 2008 STMicroelctronics.
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* Copyright (C) 2009 ST-Ericsson.
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* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
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*
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* This file is based on arm realview platform
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "setup.h"
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#include "db8500-regs.h"
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#include "id.h"
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/* Magic triggers in backup RAM */
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#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
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#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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static void wakeup_secondary(void)
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{
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struct device_node *np;
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static void __iomem *backupram;
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np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
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if (!np) {
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pr_err("No backupram base address\n");
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return;
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}
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backupram = of_iomap(np, 0);
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of_node_put(np);
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if (!backupram) {
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pr_err("No backupram remap\n");
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return;
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}
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/*
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* write the address of secondary startup into the backup ram register
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* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
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* backup ram register at offset 0x1FF0, which is what boot rom code
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* is waiting for. This will wake up the secondary core from WFE.
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*/
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writel(virt_to_phys(secondary_startup),
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backupram + UX500_CPU1_JUMPADDR_OFFSET);
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writel(0xA1FEED01,
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backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
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/* make sure write buffer is drained */
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mb();
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iounmap(backupram);
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}
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static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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static void __iomem *scu_base;
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unsigned int ncores;
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int i;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!np) {
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pr_err("No SCU base address\n");
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return;
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}
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scu_base = of_iomap(np, 0);
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of_node_put(np);
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if (!scu_base) {
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pr_err("No SCU remap\n");
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return;
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}
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scu_enable(scu_base);
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ncores = scu_get_core_count(scu_base);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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iounmap(scu_base);
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}
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static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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wakeup_secondary();
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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struct smp_operations ux500_smp_ops __initdata = {
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.smp_prepare_cpus = ux500_smp_prepare_cpus,
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.smp_boot_secondary = ux500_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = ux500_cpu_die,
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#endif
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};
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CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
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