f7d6889b79
The pixel format enumeration values used by the Tegra DSI controller don't match those defined by the DSI framework. Make sure to convert them to the internal format before writing it to the register. Signed-off-by: Thierry Reding <treding@nvidia.com>
131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DRM_TEGRA_DSI_H
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#define DRM_TEGRA_DSI_H
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#define DSI_INCR_SYNCPT 0x00
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#define DSI_INCR_SYNCPT_CONTROL 0x01
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#define DSI_INCR_SYNCPT_ERROR 0x02
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#define DSI_CTXSW 0x08
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#define DSI_RD_DATA 0x09
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#define DSI_WR_DATA 0x0a
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#define DSI_POWER_CONTROL 0x0b
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#define DSI_POWER_CONTROL_ENABLE (1 << 0)
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#define DSI_INT_ENABLE 0x0c
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#define DSI_INT_STATUS 0x0d
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#define DSI_INT_MASK 0x0e
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#define DSI_HOST_CONTROL 0x0f
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#define DSI_HOST_CONTROL_RAW (1 << 6)
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#define DSI_HOST_CONTROL_HS (1 << 5)
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#define DSI_HOST_CONTROL_BTA (1 << 2)
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#define DSI_HOST_CONTROL_CS (1 << 1)
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#define DSI_HOST_CONTROL_ECC (1 << 0)
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#define DSI_CONTROL 0x10
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#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
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#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
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#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
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#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
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#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
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#define DSI_CONTROL_DCS_ENABLE (1 << 3)
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#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
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#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
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#define DSI_CONTROL_HOST_ENABLE (1 << 0)
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#define DSI_SOL_DELAY 0x11
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#define DSI_MAX_THRESHOLD 0x12
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#define DSI_TRIGGER 0x13
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#define DSI_TX_CRC 0x14
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#define DSI_STATUS 0x15
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#define DSI_STATUS_IDLE (1 << 10)
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#define DSI_INIT_SEQ_CONTROL 0x1a
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#define DSI_INIT_SEQ_DATA_0 0x1b
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#define DSI_INIT_SEQ_DATA_1 0x1c
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#define DSI_INIT_SEQ_DATA_2 0x1d
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#define DSI_INIT_SEQ_DATA_3 0x1e
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#define DSI_INIT_SEQ_DATA_4 0x1f
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#define DSI_INIT_SEQ_DATA_5 0x20
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#define DSI_INIT_SEQ_DATA_6 0x21
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#define DSI_INIT_SEQ_DATA_7 0x22
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#define DSI_PKT_SEQ_0_LO 0x23
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#define DSI_PKT_SEQ_0_HI 0x24
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#define DSI_PKT_SEQ_1_LO 0x25
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#define DSI_PKT_SEQ_1_HI 0x26
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#define DSI_PKT_SEQ_2_LO 0x27
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#define DSI_PKT_SEQ_2_HI 0x28
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#define DSI_PKT_SEQ_3_LO 0x29
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#define DSI_PKT_SEQ_3_HI 0x2a
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#define DSI_PKT_SEQ_4_LO 0x2b
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#define DSI_PKT_SEQ_4_HI 0x2c
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#define DSI_PKT_SEQ_5_LO 0x2d
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#define DSI_PKT_SEQ_5_HI 0x2e
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#define DSI_DCS_CMDS 0x33
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#define DSI_PKT_LEN_0_1 0x34
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#define DSI_PKT_LEN_2_3 0x35
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#define DSI_PKT_LEN_4_5 0x36
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#define DSI_PKT_LEN_6_7 0x37
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#define DSI_PHY_TIMING_0 0x3c
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#define DSI_PHY_TIMING_1 0x3d
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#define DSI_PHY_TIMING_2 0x3e
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#define DSI_BTA_TIMING 0x3f
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#define DSI_TIMING_FIELD(value, period, hwinc) \
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((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
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#define DSI_TIMEOUT_0 0x44
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#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
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#define DSI_TIMEOUT_1 0x45
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#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
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#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
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#define DSI_TO_TALLY 0x46
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#define DSI_TALLY_TA(x) (((x) & 0xff) << 16)
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#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
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#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
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#define DSI_PAD_CONTROL_0 0x4b
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#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
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#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
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#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
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#define DSI_PAD_CONTROL_CD 0x4c
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#define DSI_PAD_CD_STATUS 0x4d
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#define DSI_VIDEO_MODE_CONTROL 0x4e
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#define DSI_PAD_CONTROL_1 0x4f
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#define DSI_PAD_CONTROL_2 0x50
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#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
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#define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4)
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#define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8)
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#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
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#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
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#define DSI_PAD_CONTROL_3 0x51
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#define DSI_PAD_CONTROL_4 0x52
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#define DSI_GANGED_MODE_CONTROL 0x53
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#define DSI_GANGED_MODE_START 0x54
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#define DSI_GANGED_MODE_SIZE 0x55
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#define DSI_RAW_DATA_BYTE_COUNT 0x56
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#define DSI_ULTRA_LOW_POWER_CONTROL 0x57
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#define DSI_INIT_SEQ_DATA_8 0x58
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#define DSI_INIT_SEQ_DATA_9 0x59
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#define DSI_INIT_SEQ_DATA_10 0x5a
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#define DSI_INIT_SEQ_DATA_11 0x5b
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#define DSI_INIT_SEQ_DATA_12 0x5c
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#define DSI_INIT_SEQ_DATA_13 0x5d
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#define DSI_INIT_SEQ_DATA_14 0x5e
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#define DSI_INIT_SEQ_DATA_15 0x5f
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/*
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* pixel format as used in the DSI_CONTROL_FORMAT field
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*/
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enum tegra_dsi_format {
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TEGRA_DSI_FORMAT_16P,
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TEGRA_DSI_FORMAT_18NP,
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TEGRA_DSI_FORMAT_18P,
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TEGRA_DSI_FORMAT_24P,
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};
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#endif
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