bba958783b
When using the I/O accessors in raw mode from the boot stubs we don't want to bother with any of the complexity associated with readl/writel and friends. Furthermore, utilization within the context of the host driver itself is all performed on an ioremapped window, so using the __raw variants there doesn't pose any problem either. If and when barriers need to be added in the future, these will need to be explicitly written out, but this is so far not a concern for any of the affected CPUs in question. This fixes up the link error introduced by the ARM tree via its barrier refactoring: arch/arm/boot/compressed/mmcif-sh7372.o: In function `mmcif_loader': mmcif-sh7372.c:(.text+0x9e8): undefined reference to `outer_cache Following the change in: http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6275/1 Reported-by: Simon Horman <horms@verge.net.au> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
227 lines
6.1 KiB
C
227 lines
6.1 KiB
C
/*
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* include/linux/mmc/sh_mmcif.h
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*
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* platform data for eMMC driver
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*
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* Copyright (C) 2010 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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*/
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#ifndef __SH_MMCIF_H__
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#define __SH_MMCIF_H__
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/sh_dma.h>
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/*
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* MMCIF : CE_CLK_CTRL [19:16]
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* 1000 : Peripheral clock / 512
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* 0111 : Peripheral clock / 256
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* 0110 : Peripheral clock / 128
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* 0101 : Peripheral clock / 64
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* 0100 : Peripheral clock / 32
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* 0011 : Peripheral clock / 16
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* 0010 : Peripheral clock / 8
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* 0001 : Peripheral clock / 4
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* 0000 : Peripheral clock / 2
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* 1111 : Peripheral clock (sup_pclk set '1')
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*/
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struct sh_mmcif_dma {
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struct sh_dmae_slave chan_priv_tx;
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struct sh_dmae_slave chan_priv_rx;
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};
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struct sh_mmcif_plat_data {
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void (*set_pwr)(struct platform_device *pdev, int state);
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void (*down_pwr)(struct platform_device *pdev);
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int (*get_cd)(struct platform_device *pdef);
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struct sh_mmcif_dma *dma;
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u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
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unsigned long caps;
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u32 ocr;
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};
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#define MMCIF_CE_CMD_SET 0x00000000
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#define MMCIF_CE_ARG 0x00000008
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#define MMCIF_CE_ARG_CMD12 0x0000000C
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#define MMCIF_CE_CMD_CTRL 0x00000010
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#define MMCIF_CE_BLOCK_SET 0x00000014
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#define MMCIF_CE_CLK_CTRL 0x00000018
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#define MMCIF_CE_BUF_ACC 0x0000001C
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#define MMCIF_CE_RESP3 0x00000020
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#define MMCIF_CE_RESP2 0x00000024
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#define MMCIF_CE_RESP1 0x00000028
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#define MMCIF_CE_RESP0 0x0000002C
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#define MMCIF_CE_RESP_CMD12 0x00000030
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#define MMCIF_CE_DATA 0x00000034
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#define MMCIF_CE_INT 0x00000040
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#define MMCIF_CE_INT_MASK 0x00000044
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#define MMCIF_CE_HOST_STS1 0x00000048
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#define MMCIF_CE_HOST_STS2 0x0000004C
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#define MMCIF_CE_VERSION 0x0000007C
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/* CE_BUF_ACC */
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#define BUF_ACC_DMAWEN (1 << 25)
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#define BUF_ACC_DMAREN (1 << 24)
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#define BUF_ACC_BUSW_32 (0 << 17)
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#define BUF_ACC_BUSW_16 (1 << 17)
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#define BUF_ACC_ATYP (1 << 16)
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/* CE_CLK_CTRL */
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#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
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#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
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#define CLKDIV_4 (1<<16) /* mmc clock frequency.
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* n: bus clock/(2^(n+1)) */
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#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
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#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
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#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
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(1 << 9) | (1 << 8)) /* resp busy timeout */
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#define SRWDTO_29 ((1 << 7) | (1 << 6) | \
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(1 << 5) | (1 << 4)) /* read/write timeout */
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#define SCCSTO_29 ((1 << 3) | (1 << 2) | \
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(1 << 1) | (1 << 0)) /* ccs timeout */
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/* CE_VERSION */
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#define SOFT_RST_ON (1 << 31)
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#define SOFT_RST_OFF 0
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static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
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{
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return __raw_readl(addr + reg);
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}
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static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
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{
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__raw_writel(val, addr + reg);
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}
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#define SH_MMCIF_BBS 512 /* boot block size */
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enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
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MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
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static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
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unsigned long cmd, unsigned long arg)
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{
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sh_mmcif_writel(base, MMCIF_CE_INT, 0);
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sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
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sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
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}
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static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
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{
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unsigned long tmp;
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int cnt;
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for (cnt = 0; cnt < 1000000; cnt++) {
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tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
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if (tmp & mask) {
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sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
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return 0;
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}
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}
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return -1;
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}
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static inline int sh_mmcif_boot_cmd(void __iomem *base,
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unsigned long cmd, unsigned long arg)
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{
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sh_mmcif_boot_cmd_send(base, cmd, arg);
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return sh_mmcif_boot_cmd_poll(base, 0x00010000);
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}
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static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
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unsigned int block_nr,
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unsigned long *buf)
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{
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int k;
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/* CMD13 - Status */
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sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
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if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
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return -1;
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/* CMD17 - Read */
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sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
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if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
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return -1;
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for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
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buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
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return 0;
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}
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static inline int sh_mmcif_boot_do_read(void __iomem *base,
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unsigned long first_block,
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unsigned long nr_blocks,
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void *buf)
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{
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unsigned long k;
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int ret = 0;
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/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
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sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
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CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
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SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
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/* CMD9 - Get CSD */
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sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
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/* CMD7 - Select the card */
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sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
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/* CMD16 - Set the block size */
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sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
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for (k = 0; !ret && k < nr_blocks; k++)
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ret = sh_mmcif_boot_do_read_single(base, first_block + k,
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buf + (k * SH_MMCIF_BBS));
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return ret;
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}
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static inline void sh_mmcif_boot_init(void __iomem *base)
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{
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/* reset */
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sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
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sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
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/* byte swap */
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sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
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/* Set block size in MMCIF hardware */
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sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
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/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
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sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
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CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
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SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
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/* CMD0 */
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sh_mmcif_boot_cmd(base, 0x00000040, 0);
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/* CMD1 - Get OCR */
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do {
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sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
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} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
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!= 0x80000000);
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/* CMD2 - Get CID */
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sh_mmcif_boot_cmd(base, 0x02806040, 0);
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/* CMD3 - Set card relative address */
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sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
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}
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#endif /* __SH_MMCIF_H__ */
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