e366154f70
Setting the reg-io-width to 1 byte represents more accurate description of the HW. This will fix an issue where UART driver causes kernel panic during bootup. Gregory CLEMENT traced the issue to autoconfig() in 8250.c, where the existence of FIFO is checked from UART_IIR register. The register is now read as 32-bit value as the reg-io-width is set to 4-bytes. The retuned value seems to contain bogus data for bits 31:8, causing the issue. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
156 lines
3.2 KiB
Plaintext
156 lines
3.2 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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L2: l2-cache {
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compatible = "marvell,aurora-system-cache";
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reg = <0xd0008000 0x1000>;
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cache-id-part = <0x100>;
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wt-override;
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};
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x2d0>,
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<0xd0021070 0x58>;
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};
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armada-370-xp-pmsu@d0022000 {
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compatible = "marvell,armada-370-xp-pmsu";
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reg = <0xd0022100 0x430>,
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<0xd0020800 0x20>;
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};
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soc {
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serial@d0012200 {
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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reg-io-width = <1>;
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status = "disabled";
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};
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serial@d0012300 {
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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reg-io-width = <1>;
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status = "disabled";
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};
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timer@d0020300 {
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marvell,timer-25Mhz;
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};
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coreclk: mvebu-sar@d0018230 {
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compatible = "marvell,armada-xp-core-clock";
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reg = <0xd0018230 0x08>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>;
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clocks = <&coreclk 1>;
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};
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gateclk: clock-gating-control@d0018220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0xd0018220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x500>;
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};
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ethernet@d0030000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0030000 0x2500>;
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interrupts = <12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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};
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xor@d0060900 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060900 0x100
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0xd0060b00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@d00f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xd00F0900 0x100
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0xd00F0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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usb@d0050000 {
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clocks = <&gateclk 18>;
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};
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usb@d0051000 {
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clocks = <&gateclk 19>;
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};
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usb@d0052000 {
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compatible = "marvell,orion-ehci";
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reg = <0xd0052000 0x500>;
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interrupts = <47>;
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clocks = <&gateclk 20>;
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status = "disabled";
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};
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};
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};
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