![Peter 'p2' De Schrijver](/assets/img/avatar_default.png)
This patch modifies the clock, clockdomain and OMAP3 specific powerdomain code to call the PM counter infrastructure whenever one or more powerdomains might have changed state. Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
1050 lines
29 KiB
C
1050 lines
29 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.c
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2008 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <mach/clock.h>
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#include <mach/clockdomain.h>
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#include <mach/cpu.h>
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#include <mach/prcm.h>
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#include <asm/div64.h>
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#include <mach/sdrc.h>
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#include "sdrc.h"
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#include "clock.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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/* DPLL rate rounding: minimum DPLL multiplier, divider values */
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#define DPLL_MIN_MULTIPLIER 1
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#define DPLL_MIN_DIVIDER 1
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/* Possible error results from _dpll_test_mult */
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#define DPLL_MULT_UNDERFLOW -1
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/*
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* Scale factor to mitigate roundoff errors in DPLL rate rounding.
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* The higher the scale factor, the greater the risk of arithmetic overflow,
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* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
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* must be a power of DPLL_SCALE_BASE.
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*/
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#define DPLL_SCALE_FACTOR 64
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#define DPLL_SCALE_BASE 2
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#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
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(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
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/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
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#define DPLL_FINT_BAND1_MIN 750000
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#define DPLL_FINT_BAND1_MAX 2100000
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#define DPLL_FINT_BAND2_MIN 7500000
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#define DPLL_FINT_BAND2_MAX 21000000
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/* _dpll_test_fint() return codes */
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#define DPLL_FINT_UNDERFLOW -1
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#define DPLL_FINT_INVALID -2
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u8 cpu_mask;
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/*-------------------------------------------------------------------------
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* OMAP2/3 specific clock functions
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*-------------------------------------------------------------------------*/
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/**
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* _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
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* @clk: struct clk *
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*
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* If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
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* don't take effect until the VALID_CONFIG bit is written, write the
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* VALID_CONFIG bit and wait for the write to complete. No return value.
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*/
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static void _omap2xxx_clk_commit(struct clk *clk)
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{
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if (!cpu_is_omap24xx())
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return;
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if (!(clk->flags & DELAYED_APP))
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return;
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prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
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OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
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/* OCP barrier */
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prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
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}
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/*
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* _dpll_test_fint - test whether an Fint value is valid for the DPLL
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* @clk: DPLL struct clk to test
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* @n: divider value (N) to test
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*
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* Tests whether a particular divider @n will result in a valid DPLL
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* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
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* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
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* (assuming that it is counting N upwards), or -2 if the enclosing loop
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* should skip to the next iteration (again assuming N is increasing).
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*/
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static int _dpll_test_fint(struct clk *clk, u8 n)
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{
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struct dpll_data *dd;
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long fint;
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int ret = 0;
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dd = clk->dpll_data;
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/* DPLL divider must result in a valid jitter correction val */
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fint = clk->parent->rate / (n + 1);
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if (fint < DPLL_FINT_BAND1_MIN) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"lowering max_divider\n", n);
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dd->max_divider = n;
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ret = DPLL_FINT_UNDERFLOW;
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} else if (fint > DPLL_FINT_BAND1_MAX &&
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fint < DPLL_FINT_BAND2_MIN) {
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pr_debug("rejecting n=%d due to Fint failure\n", n);
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ret = DPLL_FINT_INVALID;
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} else if (fint > DPLL_FINT_BAND2_MAX) {
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pr_debug("rejecting n=%d due to Fint failure, "
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"boosting min_divider\n", n);
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dd->min_divider = n;
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ret = DPLL_FINT_INVALID;
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}
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return ret;
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}
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/**
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* omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
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* @clk: OMAP clock struct ptr to use
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*
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* Convert a clockdomain name stored in a struct clk 'clk' into a
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* clockdomain pointer, and save it into the struct clk. Intended to be
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* called during clk_register(). No return value.
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*/
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void omap2_init_clk_clkdm(struct clk *clk)
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{
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struct clockdomain *clkdm;
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if (!clk->clkdm_name)
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return;
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clkdm = clkdm_lookup(clk->clkdm_name);
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if (clkdm) {
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pr_debug("clock: associated clk %s to clkdm %s\n",
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clk->name, clk->clkdm_name);
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clk->clkdm = clkdm;
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} else {
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pr_debug("clock: could not associate clk %s to "
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"clkdm %s\n", clk->name, clk->clkdm_name);
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}
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}
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/**
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* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
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* @clk: OMAP clock struct ptr to use
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*
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* Given a pointer to a source-selectable struct clk, read the hardware
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* register and determine what its parent is currently set to. Update the
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* clk->parent field with the appropriate clk ptr.
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*/
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void omap2_init_clksel_parent(struct clk *clk)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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if (!clk->clksel)
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return;
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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for (clks = clk->clksel; clks->parent && !found; clks++) {
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for (clkr = clks->rates; clkr->div && !found; clkr++) {
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if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
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if (clk->parent != clks->parent) {
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pr_debug("clock: inited %s parent "
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"to %s (was %s)\n",
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clk->name, clks->parent->name,
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((clk->parent) ?
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clk->parent->name : "NULL"));
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clk_reparent(clk, clks->parent);
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};
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found = 1;
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}
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}
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}
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if (!found)
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printk(KERN_ERR "clock: init parent: could not find "
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"regval %0x for clock %s\n", r, clk->name);
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return;
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}
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/**
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* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
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* @clk: struct clk * of a DPLL
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*
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* DPLLs can be locked or bypassed - basically, enabled or disabled.
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* When locked, the DPLL output depends on the M and N values. When
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* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
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* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
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* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
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* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
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* Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
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* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
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* if the clock @clk is not a DPLL.
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*/
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u32 omap2_get_dpll_rate(struct clk *clk)
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{
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long long dpll_clk;
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u32 dpll_mult, dpll_div, v;
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struct dpll_data *dd;
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dd = clk->dpll_data;
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if (!dd)
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return 0;
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/* Return bypass rate if DPLL is bypassed */
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v = __raw_readl(dd->control_reg);
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v &= dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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if (cpu_is_omap24xx()) {
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if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
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v == OMAP2XXX_EN_DPLL_FRBYPASS)
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return dd->clk_bypass->rate;
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} else if (cpu_is_omap34xx()) {
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if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
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v == OMAP3XXX_EN_DPLL_FRBYPASS)
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return dd->clk_bypass->rate;
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}
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v = __raw_readl(dd->mult_div1_reg);
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dpll_mult = v & dd->mult_mask;
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dpll_mult >>= __ffs(dd->mult_mask);
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dpll_div = v & dd->div1_mask;
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dpll_div >>= __ffs(dd->div1_mask);
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dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
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do_div(dpll_clk, dpll_div + 1);
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return dpll_clk;
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}
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/*
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* Used for clocks that have the same value as the parent clock,
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* divided by some factor
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*/
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unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
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{
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WARN_ON(!clk->fixed_div);
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return clk->parent->rate / clk->fixed_div;
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}
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/**
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* omap2_clk_dflt_find_companion - find companion clock to @clk
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* @clk: struct clk * to find the companion clock of
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* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
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* @other_bit: u8 ** to return the companion clock bit shift in
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*
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* Note: We don't need special code here for INVERT_ENABLE for the
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* time being since INVERT_ENABLE only applies to clocks enabled by
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* CM_CLKEN_PLL
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*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
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* just a matter of XORing the bits.
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*
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* Some clocks don't have companion clocks. For example, modules with
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* only an interface clock (such as MAILBOXES) don't have a companion
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* clock. Right now, this code relies on the hardware exporting a bit
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* in the correct companion register that indicates that the
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* nonexistent 'companion clock' is active. Future patches will
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* associate this type of code with per-module data structures to
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* avoid this issue, and remove the casts. No return value.
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*/
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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u8 *other_bit)
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{
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u32 r;
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/*
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* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
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* it's just a matter of XORing the bits.
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*/
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r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
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*other_reg = (__force void __iomem *)r;
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*other_bit = clk->enable_bit;
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}
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/**
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* omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
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* @clk: struct clk * to find IDLEST info for
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* @idlest_reg: void __iomem ** to return the CM_IDLEST va in
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* @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
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*
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* Return the CM_IDLEST register address and bit shift corresponding
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* to the module that "owns" this clock. This default code assumes
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* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
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* the IDLEST register address ID corresponds to the CM_*CLKEN
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* register address ID (e.g., that CM_FCLKEN2 corresponds to
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* CM_IDLEST2). This is not true for all modules. No return value.
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*/
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void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
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u8 *idlest_bit)
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{
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u32 r;
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r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
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*idlest_reg = (__force void __iomem *)r;
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*idlest_bit = clk->enable_bit;
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}
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/**
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* omap2_module_wait_ready - wait for an OMAP module to leave IDLE
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* @clk: struct clk * belonging to the module
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*
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* If the necessary clocks for the OMAP hardware IP block that
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* corresponds to clock @clk are enabled, then wait for the module to
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* indicate readiness (i.e., to leave IDLE). This code does not
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* belong in the clock code and will be moved in the medium term to
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* module-dependent code. No return value.
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*/
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static void omap2_module_wait_ready(struct clk *clk)
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{
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void __iomem *companion_reg, *idlest_reg;
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u8 other_bit, idlest_bit;
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/* Not all modules have multiple clocks that their IDLEST depends on */
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if (clk->ops->find_companion) {
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clk->ops->find_companion(clk, &companion_reg, &other_bit);
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if (!(__raw_readl(companion_reg) & (1 << other_bit)))
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return;
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}
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clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
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omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
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}
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int omap2_dflt_clk_enable(struct clk *clk)
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{
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u32 v;
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if (unlikely(clk->enable_reg == NULL)) {
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pr_err("clock.c: Enable for %s without enable code\n",
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clk->name);
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return 0; /* REVISIT: -EINVAL */
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}
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v &= ~(1 << clk->enable_bit);
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else
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v |= (1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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v = __raw_readl(clk->enable_reg); /* OCP barrier */
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if (clk->ops->find_idlest)
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omap2_module_wait_ready(clk);
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return 0;
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}
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void omap2_dflt_clk_disable(struct clk *clk)
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{
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u32 v;
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if (!clk->enable_reg) {
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/*
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* 'Independent' here refers to a clock which is not
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* controlled by its parent.
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*/
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printk(KERN_ERR "clock: clk_disable called on independent "
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"clock %s which has no enable_reg\n", clk->name);
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return;
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}
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v = __raw_readl(clk->enable_reg);
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if (clk->flags & INVERT_ENABLE)
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v |= (1 << clk->enable_bit);
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else
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v &= ~(1 << clk->enable_bit);
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__raw_writel(v, clk->enable_reg);
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/* No OCP barrier needed here since it is a disable operation */
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}
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const struct clkops clkops_omap2_dflt_wait = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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.find_companion = omap2_clk_dflt_find_companion,
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.find_idlest = omap2_clk_dflt_find_idlest,
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};
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const struct clkops clkops_omap2_dflt = {
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.enable = omap2_dflt_clk_enable,
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.disable = omap2_dflt_clk_disable,
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};
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/* Enables clock without considering parent dependencies or use count
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* REVISIT: Maybe change this to use clk->enable like on omap1?
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*/
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static int _omap2_clk_enable(struct clk *clk)
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{
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return clk->ops->enable(clk);
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}
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/* Disables clock without considering parent dependencies or use count */
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static void _omap2_clk_disable(struct clk *clk)
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{
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clk->ops->disable(clk);
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}
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void omap2_clk_disable(struct clk *clk)
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{
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if (clk->usecount > 0 && !(--clk->usecount)) {
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_omap2_clk_disable(clk);
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if (clk->parent)
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omap2_clk_disable(clk->parent);
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if (clk->clkdm)
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omap2_clkdm_clk_disable(clk->clkdm, clk);
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}
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}
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int omap2_clk_enable(struct clk *clk)
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{
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int ret = 0;
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if (clk->usecount++ == 0) {
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if (clk->clkdm)
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omap2_clkdm_clk_enable(clk->clkdm, clk);
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if (clk->parent) {
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ret = omap2_clk_enable(clk->parent);
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if (ret)
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goto err;
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}
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ret = _omap2_clk_enable(clk);
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if (ret) {
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if (clk->parent)
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omap2_clk_disable(clk->parent);
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goto err;
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}
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}
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return ret;
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err:
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if (clk->clkdm)
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omap2_clkdm_clk_disable(clk->clkdm, clk);
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clk->usecount--;
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return ret;
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}
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/*
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* Used for clocks that are part of CLKSEL_xyz governed clocks.
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* REVISIT: Maybe change to use clk->enable() functions like on omap1?
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*/
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unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
|
|
u32 div = 0;
|
|
|
|
pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
|
|
|
|
div = omap2_clksel_get_divisor(clk);
|
|
if (div == 0)
|
|
return clk->rate;
|
|
|
|
rate = clk->parent->rate / div;
|
|
|
|
pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
|
|
|
|
return rate;
|
|
}
|
|
|
|
/**
|
|
* omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
|
|
* @clk: OMAP struct clk ptr to inspect
|
|
* @src_clk: OMAP struct clk ptr of the parent clk to search for
|
|
*
|
|
* Scan the struct clksel array associated with the clock to find
|
|
* the element associated with the supplied parent clock address.
|
|
* Returns a pointer to the struct clksel on success or NULL on error.
|
|
*/
|
|
static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
|
|
struct clk *src_clk)
|
|
{
|
|
const struct clksel *clks;
|
|
|
|
if (!clk->clksel)
|
|
return NULL;
|
|
|
|
for (clks = clk->clksel; clks->parent; clks++) {
|
|
if (clks->parent == src_clk)
|
|
break; /* Found the requested parent */
|
|
}
|
|
|
|
if (!clks->parent) {
|
|
printk(KERN_ERR "clock: Could not find parent clock %s in "
|
|
"clksel array of clock %s\n", src_clk->name,
|
|
clk->name);
|
|
return NULL;
|
|
}
|
|
|
|
return clks;
|
|
}
|
|
|
|
/**
|
|
* omap2_clksel_round_rate_div - find divisor for the given clock and rate
|
|
* @clk: OMAP struct clk to use
|
|
* @target_rate: desired clock rate
|
|
* @new_div: ptr to where we should store the divisor
|
|
*
|
|
* Finds 'best' divider value in an array based on the source and target
|
|
* rates. The divider array must be sorted with smallest divider first.
|
|
* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
|
|
* they are only settable as part of virtual_prcm set.
|
|
*
|
|
* Returns the rounded clock rate or returns 0xffffffff on error.
|
|
*/
|
|
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
|
u32 *new_div)
|
|
{
|
|
unsigned long test_rate;
|
|
const struct clksel *clks;
|
|
const struct clksel_rate *clkr;
|
|
u32 last_div = 0;
|
|
|
|
pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
|
|
clk->name, target_rate);
|
|
|
|
*new_div = 1;
|
|
|
|
clks = omap2_get_clksel_by_parent(clk, clk->parent);
|
|
if (!clks)
|
|
return ~0;
|
|
|
|
for (clkr = clks->rates; clkr->div; clkr++) {
|
|
if (!(clkr->flags & cpu_mask))
|
|
continue;
|
|
|
|
/* Sanity check */
|
|
if (clkr->div <= last_div)
|
|
pr_err("clock: clksel_rate table not sorted "
|
|
"for clock %s", clk->name);
|
|
|
|
last_div = clkr->div;
|
|
|
|
test_rate = clk->parent->rate / clkr->div;
|
|
|
|
if (test_rate <= target_rate)
|
|
break; /* found it */
|
|
}
|
|
|
|
if (!clkr->div) {
|
|
pr_err("clock: Could not find divisor for target "
|
|
"rate %ld for clock %s parent %s\n", target_rate,
|
|
clk->name, clk->parent->name);
|
|
return ~0;
|
|
}
|
|
|
|
*new_div = clkr->div;
|
|
|
|
pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
|
|
(clk->parent->rate / clkr->div));
|
|
|
|
return (clk->parent->rate / clkr->div);
|
|
}
|
|
|
|
/**
|
|
* omap2_clksel_round_rate - find rounded rate for the given clock and rate
|
|
* @clk: OMAP struct clk to use
|
|
* @target_rate: desired clock rate
|
|
*
|
|
* Compatibility wrapper for OMAP clock framework
|
|
* Finds best target rate based on the source clock and possible dividers.
|
|
* rates. The divider array must be sorted with smallest divider first.
|
|
* Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
|
|
* they are only settable as part of virtual_prcm set.
|
|
*
|
|
* Returns the rounded clock rate or returns 0xffffffff on error.
|
|
*/
|
|
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
|
|
{
|
|
u32 new_div;
|
|
|
|
return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
|
|
}
|
|
|
|
|
|
/* Given a clock and a rate apply a clock specific rounding function */
|
|
long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
if (clk->round_rate)
|
|
return clk->round_rate(clk, rate);
|
|
|
|
if (clk->flags & RATE_FIXED)
|
|
printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
|
|
"on fixed-rate clock %s\n", clk->name);
|
|
|
|
return clk->rate;
|
|
}
|
|
|
|
/**
|
|
* omap2_clksel_to_divisor() - turn clksel field value into integer divider
|
|
* @clk: OMAP struct clk to use
|
|
* @field_val: register field value to find
|
|
*
|
|
* Given a struct clk of a rate-selectable clksel clock, and a register field
|
|
* value to search for, find the corresponding clock divisor. The register
|
|
* field value should be pre-masked and shifted down so the LSB is at bit 0
|
|
* before calling. Returns 0 on error
|
|
*/
|
|
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
|
|
{
|
|
const struct clksel *clks;
|
|
const struct clksel_rate *clkr;
|
|
|
|
clks = omap2_get_clksel_by_parent(clk, clk->parent);
|
|
if (!clks)
|
|
return 0;
|
|
|
|
for (clkr = clks->rates; clkr->div; clkr++) {
|
|
if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
|
|
break;
|
|
}
|
|
|
|
if (!clkr->div) {
|
|
printk(KERN_ERR "clock: Could not find fieldval %d for "
|
|
"clock %s parent %s\n", field_val, clk->name,
|
|
clk->parent->name);
|
|
return 0;
|
|
}
|
|
|
|
return clkr->div;
|
|
}
|
|
|
|
/**
|
|
* omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
|
|
* @clk: OMAP struct clk to use
|
|
* @div: integer divisor to search for
|
|
*
|
|
* Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
|
|
* find the corresponding register field value. The return register value is
|
|
* the value before left-shifting. Returns ~0 on error
|
|
*/
|
|
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
|
|
{
|
|
const struct clksel *clks;
|
|
const struct clksel_rate *clkr;
|
|
|
|
/* should never happen */
|
|
WARN_ON(div == 0);
|
|
|
|
clks = omap2_get_clksel_by_parent(clk, clk->parent);
|
|
if (!clks)
|
|
return ~0;
|
|
|
|
for (clkr = clks->rates; clkr->div; clkr++) {
|
|
if ((clkr->flags & cpu_mask) && (clkr->div == div))
|
|
break;
|
|
}
|
|
|
|
if (!clkr->div) {
|
|
printk(KERN_ERR "clock: Could not find divisor %d for "
|
|
"clock %s parent %s\n", div, clk->name,
|
|
clk->parent->name);
|
|
return ~0;
|
|
}
|
|
|
|
return clkr->val;
|
|
}
|
|
|
|
/**
|
|
* omap2_clksel_get_divisor - get current divider applied to parent clock.
|
|
* @clk: OMAP struct clk to use.
|
|
*
|
|
* Returns the integer divisor upon success or 0 on error.
|
|
*/
|
|
u32 omap2_clksel_get_divisor(struct clk *clk)
|
|
{
|
|
u32 v;
|
|
|
|
if (!clk->clksel_mask)
|
|
return 0;
|
|
|
|
v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
|
|
v >>= __ffs(clk->clksel_mask);
|
|
|
|
return omap2_clksel_to_divisor(clk, v);
|
|
}
|
|
|
|
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
u32 v, field_val, validrate, new_div = 0;
|
|
|
|
if (!clk->clksel_mask)
|
|
return -EINVAL;
|
|
|
|
validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
|
|
if (validrate != rate)
|
|
return -EINVAL;
|
|
|
|
field_val = omap2_divisor_to_clksel(clk, new_div);
|
|
if (field_val == ~0)
|
|
return -EINVAL;
|
|
|
|
v = __raw_readl(clk->clksel_reg);
|
|
v &= ~clk->clksel_mask;
|
|
v |= field_val << __ffs(clk->clksel_mask);
|
|
__raw_writel(v, clk->clksel_reg);
|
|
v = __raw_readl(clk->clksel_reg); /* OCP barrier */
|
|
|
|
clk->rate = clk->parent->rate / new_div;
|
|
|
|
_omap2xxx_clk_commit(clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* Set the clock rate for a clock source */
|
|
int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
|
|
{
|
|
int ret = -EINVAL;
|
|
|
|
pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
|
|
|
|
/* CONFIG_PARTICIPANT clocks are changed only in sets via the
|
|
rate table mechanism, driven by mpu_speed */
|
|
if (clk->flags & CONFIG_PARTICIPANT)
|
|
return -EINVAL;
|
|
|
|
/* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
|
|
if (clk->set_rate)
|
|
ret = clk->set_rate(clk, rate);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Converts encoded control register address into a full address
|
|
* On error, the return value (parent_div) will be 0.
|
|
*/
|
|
static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
|
|
u32 *field_val)
|
|
{
|
|
const struct clksel *clks;
|
|
const struct clksel_rate *clkr;
|
|
|
|
clks = omap2_get_clksel_by_parent(clk, src_clk);
|
|
if (!clks)
|
|
return 0;
|
|
|
|
for (clkr = clks->rates; clkr->div; clkr++) {
|
|
if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
|
|
break; /* Found the default rate for this platform */
|
|
}
|
|
|
|
if (!clkr->div) {
|
|
printk(KERN_ERR "clock: Could not find default rate for "
|
|
"clock %s parent %s\n", clk->name,
|
|
src_clk->parent->name);
|
|
return 0;
|
|
}
|
|
|
|
/* Should never happen. Add a clksel mask to the struct clk. */
|
|
WARN_ON(clk->clksel_mask == 0);
|
|
|
|
*field_val = clkr->val;
|
|
|
|
return clkr->div;
|
|
}
|
|
|
|
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
|
|
{
|
|
u32 field_val, v, parent_div;
|
|
|
|
if (clk->flags & CONFIG_PARTICIPANT)
|
|
return -EINVAL;
|
|
|
|
if (!clk->clksel)
|
|
return -EINVAL;
|
|
|
|
parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
|
|
if (!parent_div)
|
|
return -EINVAL;
|
|
|
|
/* Set new source value (previous dividers if any in effect) */
|
|
v = __raw_readl(clk->clksel_reg);
|
|
v &= ~clk->clksel_mask;
|
|
v |= field_val << __ffs(clk->clksel_mask);
|
|
__raw_writel(v, clk->clksel_reg);
|
|
v = __raw_readl(clk->clksel_reg); /* OCP barrier */
|
|
|
|
_omap2xxx_clk_commit(clk);
|
|
|
|
clk_reparent(clk, new_parent);
|
|
|
|
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
|
|
clk->rate = new_parent->rate;
|
|
|
|
if (parent_div > 0)
|
|
clk->rate /= parent_div;
|
|
|
|
pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
|
|
clk->name, clk->parent->name, clk->rate);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* DPLL rate rounding code */
|
|
|
|
/**
|
|
* omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
|
|
* @clk: struct clk * of the DPLL
|
|
* @tolerance: maximum rate error tolerance
|
|
*
|
|
* Set the maximum DPLL rate error tolerance for the rate rounding
|
|
* algorithm. The rate tolerance is an attempt to balance DPLL power
|
|
* saving (the least divider value "n") vs. rate fidelity (the least
|
|
* difference between the desired DPLL target rate and the rounded
|
|
* rate out of the algorithm). So, increasing the tolerance is likely
|
|
* to decrease DPLL power consumption and increase DPLL rate error.
|
|
* Returns -EINVAL if provided a null clock ptr or a clk that is not a
|
|
* DPLL; or 0 upon success.
|
|
*/
|
|
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
|
|
{
|
|
if (!clk || !clk->dpll_data)
|
|
return -EINVAL;
|
|
|
|
clk->dpll_data->rate_tolerance = tolerance;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
|
|
unsigned int m, unsigned int n)
|
|
{
|
|
unsigned long long num;
|
|
|
|
num = (unsigned long long)parent_rate * m;
|
|
do_div(num, n);
|
|
return num;
|
|
}
|
|
|
|
/*
|
|
* _dpll_test_mult - test a DPLL multiplier value
|
|
* @m: pointer to the DPLL m (multiplier) value under test
|
|
* @n: current DPLL n (divider) value under test
|
|
* @new_rate: pointer to storage for the resulting rounded rate
|
|
* @target_rate: the desired DPLL rate
|
|
* @parent_rate: the DPLL's parent clock rate
|
|
*
|
|
* This code tests a DPLL multiplier value, ensuring that the
|
|
* resulting rate will not be higher than the target_rate, and that
|
|
* the multiplier value itself is valid for the DPLL. Initially, the
|
|
* integer pointed to by the m argument should be prescaled by
|
|
* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
|
|
* a non-scaled m upon return. This non-scaled m will result in a
|
|
* new_rate as close as possible to target_rate (but not greater than
|
|
* target_rate) given the current (parent_rate, n, prescaled m)
|
|
* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
|
|
* non-scaled m attempted to underflow, which can allow the calling
|
|
* function to bail out early; or 0 upon success.
|
|
*/
|
|
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
|
|
unsigned long target_rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
int r = 0, carry = 0;
|
|
|
|
/* Unscale m and round if necessary */
|
|
if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
|
|
carry = 1;
|
|
*m = (*m / DPLL_SCALE_FACTOR) + carry;
|
|
|
|
/*
|
|
* The new rate must be <= the target rate to avoid programming
|
|
* a rate that is impossible for the hardware to handle
|
|
*/
|
|
*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
|
|
if (*new_rate > target_rate) {
|
|
(*m)--;
|
|
*new_rate = 0;
|
|
}
|
|
|
|
/* Guard against m underflow */
|
|
if (*m < DPLL_MIN_MULTIPLIER) {
|
|
*m = DPLL_MIN_MULTIPLIER;
|
|
*new_rate = 0;
|
|
r = DPLL_MULT_UNDERFLOW;
|
|
}
|
|
|
|
if (*new_rate == 0)
|
|
*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
|
|
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
|
|
* @clk: struct clk * for a DPLL
|
|
* @target_rate: desired DPLL clock rate
|
|
*
|
|
* Given a DPLL, a desired target rate, and a rate tolerance, round
|
|
* the target rate to a possible, programmable rate for this DPLL.
|
|
* Rate tolerance is assumed to be set by the caller before this
|
|
* function is called. Attempts to select the minimum possible n
|
|
* within the tolerance to reduce power consumption. Stores the
|
|
* computed (m, n) in the DPLL's dpll_data structure so set_rate()
|
|
* will not need to call this (expensive) function again. Returns ~0
|
|
* if the target rate cannot be rounded, either because the rate is
|
|
* too low or because the rate tolerance is set too tightly; or the
|
|
* rounded rate upon success.
|
|
*/
|
|
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
|
|
{
|
|
int m, n, r, e, scaled_max_m;
|
|
unsigned long scaled_rt_rp, new_rate;
|
|
int min_e = -1, min_e_m = -1, min_e_n = -1;
|
|
struct dpll_data *dd;
|
|
|
|
if (!clk || !clk->dpll_data)
|
|
return ~0;
|
|
|
|
dd = clk->dpll_data;
|
|
|
|
pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
|
|
"%ld\n", clk->name, target_rate);
|
|
|
|
scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
|
|
scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
|
|
|
|
dd->last_rounded_rate = 0;
|
|
|
|
for (n = dd->min_divider; n <= dd->max_divider; n++) {
|
|
|
|
/* Is the (input clk, divider) pair valid for the DPLL? */
|
|
r = _dpll_test_fint(clk, n);
|
|
if (r == DPLL_FINT_UNDERFLOW)
|
|
break;
|
|
else if (r == DPLL_FINT_INVALID)
|
|
continue;
|
|
|
|
/* Compute the scaled DPLL multiplier, based on the divider */
|
|
m = scaled_rt_rp * n;
|
|
|
|
/*
|
|
* Since we're counting n up, a m overflow means we
|
|
* can bail out completely (since as n increases in
|
|
* the next iteration, there's no way that m can
|
|
* increase beyond the current m)
|
|
*/
|
|
if (m > scaled_max_m)
|
|
break;
|
|
|
|
r = _dpll_test_mult(&m, n, &new_rate, target_rate,
|
|
dd->clk_ref->rate);
|
|
|
|
/* m can't be set low enough for this n - try with a larger n */
|
|
if (r == DPLL_MULT_UNDERFLOW)
|
|
continue;
|
|
|
|
e = target_rate - new_rate;
|
|
pr_debug("clock: n = %d: m = %d: rate error is %d "
|
|
"(new_rate = %ld)\n", n, m, e, new_rate);
|
|
|
|
if (min_e == -1 ||
|
|
min_e >= (int)(abs(e) - dd->rate_tolerance)) {
|
|
min_e = e;
|
|
min_e_m = m;
|
|
min_e_n = n;
|
|
|
|
pr_debug("clock: found new least error %d\n", min_e);
|
|
|
|
/* We found good settings -- bail out now */
|
|
if (min_e <= dd->rate_tolerance)
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (min_e < 0) {
|
|
pr_debug("clock: error: target rate or tolerance too low\n");
|
|
return ~0;
|
|
}
|
|
|
|
dd->last_rounded_m = min_e_m;
|
|
dd->last_rounded_n = min_e_n;
|
|
dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
|
|
min_e_m, min_e_n);
|
|
|
|
pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
|
|
min_e, min_e_m, min_e_n);
|
|
pr_debug("clock: final rate: %ld (target rate: %ld)\n",
|
|
dd->last_rounded_rate, target_rate);
|
|
|
|
return dd->last_rounded_rate;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------
|
|
* Omap2 clock reset and init functions
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
|
void omap2_clk_disable_unused(struct clk *clk)
|
|
{
|
|
u32 regval32, v;
|
|
|
|
v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
|
|
|
|
regval32 = __raw_readl(clk->enable_reg);
|
|
if ((regval32 & (1 << clk->enable_bit)) == v)
|
|
return;
|
|
|
|
printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
|
|
if (cpu_is_omap34xx()) {
|
|
omap2_clk_enable(clk);
|
|
omap2_clk_disable(clk);
|
|
} else
|
|
_omap2_clk_disable(clk);
|
|
if (clk->clkdm != NULL)
|
|
pwrdm_clkdm_state_switch(clk->clkdm);
|
|
}
|
|
#endif
|