![Boris BREZILLON](/assets/img/avatar_default.png)
Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of the AIC block) drivers. Put common code in irq-atmel-aic-common.c/.h so that both driver can access shared functions (this will ease maintenance). These drivers are only compatible with dt enabled board and replace the old implementation found in arch/arm/mach-at91/irq.c. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
208 lines
4.6 KiB
C
208 lines
4.6 KiB
C
/*
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* Atmel AT91 common AIC (Advanced Interrupt Controller) code shared by
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* irq-atmel-aic and irq-atmel-aic5 drivers
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "irq-atmel-aic-common.h"
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#define AT91_AIC_PRIOR GENMASK(2, 0)
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#define AT91_AIC_IRQ_MIN_PRIORITY 0
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#define AT91_AIC_IRQ_MAX_PRIORITY 7
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#define AT91_AIC_SRCTYPE GENMASK(7, 6)
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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struct aic_chip_data {
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u32 ext_irqs;
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};
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static void aic_common_shutdown(struct irq_data *d)
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{
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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ct->chip.irq_mask(d);
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}
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int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct aic_chip_data *aic = gc->private;
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unsigned aic_type;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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aic_type = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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aic_type = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if (!(d->mask & aic->ext_irqs))
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return -EINVAL;
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aic_type = AT91_AIC_SRCTYPE_LOW;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if (!(d->mask & aic->ext_irqs))
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return -EINVAL;
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aic_type = AT91_AIC_SRCTYPE_FALLING;
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break;
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default:
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return -EINVAL;
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}
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*val &= AT91_AIC_SRCTYPE;
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*val |= aic_type;
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return 0;
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}
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int aic_common_set_priority(int priority, unsigned *val)
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{
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if (priority < AT91_AIC_IRQ_MIN_PRIORITY ||
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priority > AT91_AIC_IRQ_MAX_PRIORITY)
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return -EINVAL;
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*val &= AT91_AIC_PRIOR;
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*val |= priority;
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return 0;
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}
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int aic_common_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec,
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unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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if (WARN_ON(intsize < 3))
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return -EINVAL;
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if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) ||
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(intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static void __init aic_common_ext_irq_of_init(struct irq_domain *domain)
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{
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struct device_node *node = domain->of_node;
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struct irq_chip_generic *gc;
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struct aic_chip_data *aic;
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struct property *prop;
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const __be32 *p;
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u32 hwirq;
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gc = irq_get_domain_generic_chip(domain, 0);
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aic = gc->private;
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aic->ext_irqs |= 1;
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of_property_for_each_u32(node, "atmel,external-irqs", prop, p, hwirq) {
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gc = irq_get_domain_generic_chip(domain, hwirq);
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if (!gc) {
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pr_warn("AIC: external irq %d >= %d skip it\n",
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hwirq, domain->revmap_size);
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continue;
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}
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aic = gc->private;
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aic->ext_irqs |= (1 << (hwirq % 32));
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}
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}
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struct irq_domain *__init aic_common_of_init(struct device_node *node,
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const struct irq_domain_ops *ops,
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const char *name, int nirqs)
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{
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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struct aic_chip_data *aic;
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void __iomem *reg_base;
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int nchips;
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int ret;
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int i;
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nchips = DIV_ROUND_UP(nirqs, 32);
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reg_base = of_iomap(node, 0);
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if (!reg_base)
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return ERR_PTR(-ENOMEM);
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aic = kcalloc(nchips, sizeof(*aic), GFP_KERNEL);
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if (!aic) {
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ret = -ENOMEM;
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goto err_iounmap;
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}
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domain = irq_domain_add_linear(node, nchips * 32, ops, aic);
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if (!domain) {
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ret = -ENOMEM;
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goto err_free_aic;
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}
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ret = irq_alloc_domain_generic_chips(domain, 32, 1, name,
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handle_level_irq, 0, 0,
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IRQCHIP_SKIP_SET_WAKE);
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if (ret)
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goto err_domain_remove;
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for (i = 0; i < nchips; i++) {
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gc = irq_get_domain_generic_chip(domain, i * 32);
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gc->reg_base = reg_base;
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gc->unused = 0;
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gc->wake_enabled = ~0;
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gc->chip_types[0].type = IRQ_TYPE_SENSE_MASK;
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gc->chip_types[0].handler = handle_fasteoi_irq;
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gc->chip_types[0].chip.irq_eoi = irq_gc_eoi;
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gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
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gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown;
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gc->private = &aic[i];
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}
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aic_common_ext_irq_of_init(domain);
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return domain;
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err_domain_remove:
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irq_domain_remove(domain);
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err_free_aic:
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kfree(aic);
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err_iounmap:
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iounmap(reg_base);
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return ERR_PTR(ret);
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}
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