67 lines
2.6 KiB
Plaintext
67 lines
2.6 KiB
Plaintext
* Freescale enhanced Direct Memory Access(eDMA-v3) Controller
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The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated
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on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by
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programmble memory-mapped registers. Specific DMA request source has fixed channel.
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* eDMA Controller
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Required properties:
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- compatible :
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- "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC
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- "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM
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- reg : Specifies base physical address(s) and size of the eDMA channel registers.
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Each eDMA channel has separated register's address and size.
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- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
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- interrupt-names : Should contain:
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"edma-chan12-tx" - the channel12 transmission interrupt
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- #dma-cells : Must be <4>.
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The 1st cell specifies the channel ID.
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The 2nd cell specifies the channel priority.
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The 3rd cell specifies the channel type like for transmit or receive:
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0: transmit, 1: receive.
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The 4th cell specifies the local access or remote access:
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0: local, 1: remote.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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Examples:
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edma0: dma-controller@40018000 {
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compatible = "fsl,imx8qm-edma";
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reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
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<0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
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<0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
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<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
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#dma-cells = <4>;
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dma-channels = <4>;
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interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-chan12-tx", "edma-chan13-tx",
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"edma-chan14-tx", "edma-chan15-tx";
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status = "okay";
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};
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* DMA clients
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DMA client drivers that uses the DMA function must use the format described
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in the dma.txt file, using a three-cell specifier for each channel: the 1st
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specifies the channel number, the 2nd specifies the priority, and the 3rd
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specifies the channel type is for transmit or receive: 0: transmit, 1: receive.
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Examples:
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lpuart1: serial@5a070000 {
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compatible = "fsl,imx8qm-lpuart";
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reg = <0x0 0x5a070000 0x0 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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clocks = <&clk IMX8QM_UART1_CLK>;
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clock-names = "ipg";
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assigned-clock-names = <&clk IMX8QM_UART1_CLK>;
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assigned-clock-rates = <80000000>;
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power-domains = <&pd_dma_lpuart1>;
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dma-names = "tx","rx";
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dmas = <&edma0 15 0 0 0>,
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<&edma0 14 0 1 0>;
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status = "disabled";
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};
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