5d5b7803c4
When crtc/timing is disabled on boot the dig block should be stopped in order ignore timing from crtc, reset the steering fifo otherwise we get display corruption or hung in dp sst mode. v2: agd: fix coding style Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
316 lines
17 KiB
C
316 lines
17 KiB
C
/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef __EVERGREEN_REG_H__
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#define __EVERGREEN_REG_H__
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/* trinity */
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#define TN_SMC_IND_INDEX_0 0x200
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#define TN_SMC_IND_DATA_0 0x204
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/* evergreen */
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#define EVERGREEN_PIF_PHY0_INDEX 0x8
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#define EVERGREEN_PIF_PHY0_DATA 0xc
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#define EVERGREEN_PIF_PHY1_INDEX 0x10
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#define EVERGREEN_PIF_PHY1_DATA 0x14
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#define EVERGREEN_MM_INDEX_HI 0x18
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
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#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
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#define EVERGREEN_D3VGA_CONTROL 0x3e0
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#define EVERGREEN_D4VGA_CONTROL 0x3e4
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#define EVERGREEN_D5VGA_CONTROL 0x3e8
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#define EVERGREEN_D6VGA_CONTROL 0x3ec
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#define EVERGREEN_P1PLL_SS_CNTL 0x414
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#define EVERGREEN_P2PLL_SS_CNTL 0x454
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# define EVERGREEN_PxPLL_SS_EN (1 << 12)
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#define EVERGREEN_AUDIO_PLL1_MUL 0x5b0
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#define EVERGREEN_AUDIO_PLL1_DIV 0x5b4
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#define EVERGREEN_AUDIO_PLL1_UNK 0x5bc
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#define EVERGREEN_CG_IND_ADDR 0x8f8
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#define EVERGREEN_CG_IND_DATA 0x8fc
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#define EVERGREEN_AUDIO_ENABLE 0x5e78
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#define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0
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/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
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#define EVERGREEN_GRPH_ENABLE 0x6800
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#define EVERGREEN_GRPH_CONTROL 0x6804
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# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
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# define EVERGREEN_GRPH_DEPTH_8BPP 0
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# define EVERGREEN_GRPH_DEPTH_16BPP 1
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# define EVERGREEN_GRPH_DEPTH_32BPP 2
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# define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
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# define EVERGREEN_ADDR_SURF_2_BANK 0
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# define EVERGREEN_ADDR_SURF_4_BANK 1
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# define EVERGREEN_ADDR_SURF_8_BANK 2
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# define EVERGREEN_ADDR_SURF_16_BANK 3
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# define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4)
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# define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
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# define EVERGREEN_ADDR_SURF_BANK_WIDTH_1 0
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# define EVERGREEN_ADDR_SURF_BANK_WIDTH_2 1
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# define EVERGREEN_ADDR_SURF_BANK_WIDTH_4 2
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# define EVERGREEN_ADDR_SURF_BANK_WIDTH_8 3
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# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
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/* 8 BPP */
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# define EVERGREEN_GRPH_FORMAT_INDEXED 0
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/* 16 BPP */
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# define EVERGREEN_GRPH_FORMAT_ARGB1555 0
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# define EVERGREEN_GRPH_FORMAT_ARGB565 1
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# define EVERGREEN_GRPH_FORMAT_ARGB4444 2
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# define EVERGREEN_GRPH_FORMAT_AI88 3
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# define EVERGREEN_GRPH_FORMAT_MONO16 4
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# define EVERGREEN_GRPH_FORMAT_BGRA5551 5
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/* 32 BPP */
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# define EVERGREEN_GRPH_FORMAT_ARGB8888 0
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# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
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# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
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# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3
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# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4
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# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
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# define EVERGREEN_GRPH_FORMAT_RGB111110 6
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# define EVERGREEN_GRPH_FORMAT_BGR101111 7
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# define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
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# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_1 0
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# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_2 1
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# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_4 2
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# define EVERGREEN_ADDR_SURF_BANK_HEIGHT_8 3
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# define EVERGREEN_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_64B 0
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_128B 1
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_256B 2
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_512B 3
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB 4
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB 5
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# define EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB 6
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# define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
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# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1 0
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# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2 1
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# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4 2
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# define EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8 3
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# define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
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# define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL 0
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# define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED 1
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# define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1 2
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# define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1 4
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#define EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL 0x6808
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# define EVERGREEN_LUT_10BIT_BYPASS_EN (1 << 8)
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#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
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# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
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# define EVERGREEN_GRPH_ENDIAN_NONE 0
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# define EVERGREEN_GRPH_ENDIAN_8IN16 1
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# define EVERGREEN_GRPH_ENDIAN_8IN32 2
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# define EVERGREEN_GRPH_ENDIAN_8IN64 3
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# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
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# define EVERGREEN_GRPH_RED_SEL_R 0
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# define EVERGREEN_GRPH_RED_SEL_G 1
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# define EVERGREEN_GRPH_RED_SEL_B 2
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# define EVERGREEN_GRPH_RED_SEL_A 3
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# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
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# define EVERGREEN_GRPH_GREEN_SEL_G 0
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# define EVERGREEN_GRPH_GREEN_SEL_B 1
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# define EVERGREEN_GRPH_GREEN_SEL_A 2
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# define EVERGREEN_GRPH_GREEN_SEL_R 3
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# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
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# define EVERGREEN_GRPH_BLUE_SEL_B 0
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# define EVERGREEN_GRPH_BLUE_SEL_A 1
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# define EVERGREEN_GRPH_BLUE_SEL_R 2
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# define EVERGREEN_GRPH_BLUE_SEL_G 3
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# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
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# define EVERGREEN_GRPH_ALPHA_SEL_A 0
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# define EVERGREEN_GRPH_ALPHA_SEL_R 1
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# define EVERGREEN_GRPH_ALPHA_SEL_G 2
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# define EVERGREEN_GRPH_ALPHA_SEL_B 3
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#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810
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#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814
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# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0)
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# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00
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#define EVERGREEN_GRPH_PITCH 0x6818
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#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c
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#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820
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#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824
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#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828
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#define EVERGREEN_GRPH_X_START 0x682c
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#define EVERGREEN_GRPH_Y_START 0x6830
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#define EVERGREEN_GRPH_X_END 0x6834
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#define EVERGREEN_GRPH_Y_END 0x6838
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#define EVERGREEN_GRPH_UPDATE 0x6844
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# define EVERGREEN_GRPH_SURFACE_UPDATE_PENDING (1 << 2)
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# define EVERGREEN_GRPH_UPDATE_LOCK (1 << 16)
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#define EVERGREEN_GRPH_FLIP_CONTROL 0x6848
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# define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
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/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
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#define EVERGREEN_CUR_CONTROL 0x6998
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# define EVERGREEN_CURSOR_EN (1 << 0)
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# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
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# define EVERGREEN_CURSOR_MONO 0
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# define EVERGREEN_CURSOR_24_1 1
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# define EVERGREEN_CURSOR_24_8_PRE_MULT 2
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# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3
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# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
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# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
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# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
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# define EVERGREEN_CURSOR_URGENT_ALWAYS 0
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# define EVERGREEN_CURSOR_URGENT_1_8 1
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# define EVERGREEN_CURSOR_URGENT_1_4 2
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# define EVERGREEN_CURSOR_URGENT_3_8 3
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# define EVERGREEN_CURSOR_URGENT_1_2 4
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#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c
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# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000
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#define EVERGREEN_CUR_SIZE 0x69a0
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#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4
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#define EVERGREEN_CUR_POSITION 0x69a8
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#define EVERGREEN_CUR_HOT_SPOT 0x69ac
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#define EVERGREEN_CUR_COLOR1 0x69b0
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#define EVERGREEN_CUR_COLOR2 0x69b4
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#define EVERGREEN_CUR_UPDATE 0x69b8
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# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
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# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
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# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
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# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
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/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */
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#define EVERGREEN_DC_LUT_RW_MODE 0x69e0
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#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4
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#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8
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#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec
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#define EVERGREEN_DC_LUT_30_COLOR 0x69f0
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#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4
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#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8
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#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc
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#define EVERGREEN_DC_LUT_CONTROL 0x6a00
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#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04
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#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08
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#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c
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#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10
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#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14
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#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18
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#define EVERGREEN_DATA_FORMAT 0x6b00
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# define EVERGREEN_INTERLEAVE_EN (1 << 0)
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#define EVERGREEN_DESKTOP_HEIGHT 0x6b04
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#define EVERGREEN_VLINE_START_END 0x6b08
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#define EVERGREEN_VLINE_STATUS 0x6bb8
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# define EVERGREEN_VLINE_STAT (1 << 12)
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#define EVERGREEN_VIEWPORT_START 0x6d70
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#define EVERGREEN_VIEWPORT_SIZE 0x6d74
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/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
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#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)
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#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0)
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#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0)
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#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0)
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#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0)
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#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0)
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/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
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#define EVERGREEN_CRTC_V_BLANK_START_END 0x6e34
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#define EVERGREEN_CRTC_CONTROL 0x6e70
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# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
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# define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
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#define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74
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# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8)
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#define EVERGREEN_CRTC_STATUS 0x6e8c
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# define EVERGREEN_CRTC_V_BLANK (1 << 0)
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#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
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#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0
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#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
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#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
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#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
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#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
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#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
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#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8
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#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc
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/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
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#define EVERGREEN_HDMI_BASE 0x7030
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/*DIG block*/
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#define NI_DIG0_REGISTER_OFFSET (0x7000 - 0x7000)
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#define NI_DIG1_REGISTER_OFFSET (0x7C00 - 0x7000)
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#define NI_DIG2_REGISTER_OFFSET (0x10800 - 0x7000)
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#define NI_DIG3_REGISTER_OFFSET (0x11400 - 0x7000)
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#define NI_DIG4_REGISTER_OFFSET (0x12000 - 0x7000)
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#define NI_DIG5_REGISTER_OFFSET (0x12C00 - 0x7000)
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#define NI_DIG_FE_CNTL 0x7000
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# define NI_DIG_FE_CNTL_SOURCE_SELECT(x) ((x) & 0x3)
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# define NI_DIG_FE_CNTL_SYMCLK_FE_ON (1<<24)
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#define NI_DIG_BE_CNTL 0x7140
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# define NI_DIG_BE_CNTL_FE_SOURCE_SELECT(x) (((x) >> 8 ) & 0x3F)
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# define NI_DIG_FE_CNTL_MODE(x) (((x) >> 16) & 0x7 )
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#define NI_DIG_BE_EN_CNTL 0x7144
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# define NI_DIG_BE_EN_CNTL_ENABLE (1 << 0)
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# define NI_DIG_BE_EN_CNTL_SYMBCLK_ON (1 << 8)
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# define NI_DIG_BE_DPSST 0
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/* Display Port block */
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#define EVERGREEN_DP0_REGISTER_OFFSET (0x730C - 0x730C)
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#define EVERGREEN_DP1_REGISTER_OFFSET (0x7F0C - 0x730C)
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#define EVERGREEN_DP2_REGISTER_OFFSET (0x10B0C - 0x730C)
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#define EVERGREEN_DP3_REGISTER_OFFSET (0x1170C - 0x730C)
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#define EVERGREEN_DP4_REGISTER_OFFSET (0x1230C - 0x730C)
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#define EVERGREEN_DP5_REGISTER_OFFSET (0x12F0C - 0x730C)
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#define EVERGREEN_DP_VID_STREAM_CNTL 0x730C
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# define EVERGREEN_DP_VID_STREAM_CNTL_ENABLE (1 << 0)
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# define EVERGREEN_DP_VID_STREAM_STATUS (1 <<16)
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#define EVERGREEN_DP_STEER_FIFO 0x7310
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# define EVERGREEN_DP_STEER_FIFO_RESET (1 << 0)
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#define EVERGREEN_DP_SEC_CNTL 0x7280
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# define EVERGREEN_DP_SEC_STREAM_ENABLE (1 << 0)
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# define EVERGREEN_DP_SEC_ASP_ENABLE (1 << 4)
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# define EVERGREEN_DP_SEC_ATP_ENABLE (1 << 8)
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# define EVERGREEN_DP_SEC_AIP_ENABLE (1 << 12)
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# define EVERGREEN_DP_SEC_GSP_ENABLE (1 << 20)
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# define EVERGREEN_DP_SEC_AVI_ENABLE (1 << 24)
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# define EVERGREEN_DP_SEC_MPG_ENABLE (1 << 28)
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#define EVERGREEN_DP_SEC_TIMESTAMP 0x72a4
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# define EVERGREEN_DP_SEC_TIMESTAMP_MODE(x) (((x) & 0x3) << 0)
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#define EVERGREEN_DP_SEC_AUD_N 0x7294
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# define EVERGREEN_DP_SEC_N_BASE_MULTIPLE(x) (((x) & 0xf) << 24)
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# define EVERGREEN_DP_SEC_SS_EN (1 << 28)
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/*DCIO_UNIPHY block*/
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#define NI_DCIO_UNIPHY0_UNIPHY_TX_CONTROL1 (0x6600 -0x6600)
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#define NI_DCIO_UNIPHY1_UNIPHY_TX_CONTROL1 (0x6640 -0x6600)
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#define NI_DCIO_UNIPHY2_UNIPHY_TX_CONTROL1 (0x6680 - 0x6600)
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#define NI_DCIO_UNIPHY3_UNIPHY_TX_CONTROL1 (0x66C0 - 0x6600)
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#define NI_DCIO_UNIPHY4_UNIPHY_TX_CONTROL1 (0x6700 - 0x6600)
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#define NI_DCIO_UNIPHY5_UNIPHY_TX_CONTROL1 (0x6740 - 0x6600)
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#define NI_DCIO_UNIPHY0_PLL_CONTROL1 0x6618
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# define NI_DCIO_UNIPHY0_PLL_CONTROL1_ENABLE (1 << 0)
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#endif
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