![Paulo Zanoni](/assets/img/avatar_default.png)
Caught by "make W=1 drivers/gpu/drm/i915/". Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
1276 lines
36 KiB
C
1276 lines
36 KiB
C
/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
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{
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return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
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}
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static void
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assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
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{
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struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t enabled_bits;
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enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
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"HDMI port enabled, expecting disabled\n");
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}
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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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struct intel_digital_port *intel_dig_port =
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container_of(encoder, struct intel_digital_port, base.base);
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return &intel_dig_port->hdmi;
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}
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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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{
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return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
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}
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static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
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{
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_SELECT_AVI;
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_SELECT_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
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{
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI;
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
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{
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI_HSW;
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case HDMI_INFOFRAME_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD_HSW;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
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enum transcoder cpu_transcoder)
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{
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switch (type) {
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case HDMI_INFOFRAME_TYPE_AVI:
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return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
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case HDMI_INFOFRAME_TYPE_SPD:
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return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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return 0;
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}
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}
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static void g4x_write_infoframe(struct drm_encoder *encoder,
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val = I915_READ(VIDEO_DIP_CTL);
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int i;
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(VIDEO_DIP_CTL, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VIDEO_DIP_DATA, *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VIDEO_DIP_DATA, 0);
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mmiowb();
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(VIDEO_DIP_CTL, val);
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POSTING_READ(VIDEO_DIP_CTL);
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}
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static void ibx_write_infoframe(struct drm_encoder *encoder,
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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static void cpt_write_infoframe(struct drm_encoder *encoder,
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(type);
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/* The DIP control register spec says that we need to update the AVI
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* infoframe without clearing its enable bit */
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if (type != HDMI_INFOFRAME_TYPE_AVI)
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(type);
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val &= ~g4x_infoframe_enable(type);
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I915_WRITE(reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(type);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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static void hsw_write_infoframe(struct drm_encoder *encoder,
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enum hdmi_infoframe_type type,
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const uint8_t *frame, ssize_t len)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
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u32 data_reg;
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int i;
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u32 val = I915_READ(ctl_reg);
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data_reg = hsw_infoframe_data_reg(type,
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intel_crtc->config.cpu_transcoder);
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if (data_reg == 0)
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return;
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val &= ~hsw_infoframe_enable(type);
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I915_WRITE(ctl_reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(data_reg + i, *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(data_reg + i, 0);
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mmiowb();
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val |= hsw_infoframe_enable(type);
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I915_WRITE(ctl_reg, val);
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POSTING_READ(ctl_reg);
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}
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/*
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* The data we write to the DIP data buffer registers is 1 byte bigger than the
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* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
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* at 0). It's also a byte used by DisplayPort so the same DIP registers can be
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* used for both technologies.
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*
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* DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
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* DW1: DB3 | DB2 | DB1 | DB0
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* DW2: DB7 | DB6 | DB5 | DB4
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* DW3: ...
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*
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* (HB is Header Byte, DB is Data Byte)
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*
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* The hdmi pack() functions don't know about that hardware specific hole so we
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* trick them by giving an offset into the buffer and moving back the header
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* bytes by one.
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*/
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static void intel_write_infoframe(struct drm_encoder *encoder,
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union hdmi_infoframe *frame)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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uint8_t buffer[VIDEO_DIP_DATA_SIZE];
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ssize_t len;
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/* see comment above for the reason for this offset */
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len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
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if (len < 0)
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return;
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/* Insert the 'hole' (see big comment above) at position 3 */
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buffer[0] = buffer[1];
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buffer[1] = buffer[2];
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buffer[2] = buffer[3];
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buffer[3] = 0;
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len++;
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intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
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}
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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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union hdmi_infoframe frame;
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int ret;
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ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
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adjusted_mode);
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if (ret < 0) {
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DRM_ERROR("couldn't fill AVI infoframe\n");
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return;
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}
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if (intel_hdmi->rgb_quant_range_selectable) {
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if (intel_crtc->config.limited_color_range)
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frame.avi.quantization_range =
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HDMI_QUANTIZATION_RANGE_LIMITED;
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else
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frame.avi.quantization_range =
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HDMI_QUANTIZATION_RANGE_FULL;
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}
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intel_write_infoframe(encoder, &frame);
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}
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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
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union hdmi_infoframe frame;
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int ret;
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ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
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if (ret < 0) {
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DRM_ERROR("couldn't fill SPD infoframe\n");
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return;
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}
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frame.spd.sdi = HDMI_SPD_SDI_PC;
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intel_write_infoframe(encoder, &frame);
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}
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static void g4x_set_infoframes(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
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struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
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u32 reg = VIDEO_DIP_CTL;
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u32 val = I915_READ(reg);
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u32 port;
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assert_hdmi_port_disabled(intel_hdmi);
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/* If the registers were not initialized yet, they might be zeroes,
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* which means we're selecting the AVI DIP and we're setting its
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* frequency to once. This seems to really confuse the HW and make
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* things stop working (the register spec says the AVI always needs to
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* be sent every VSync). So here we avoid writing to the register more
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* than we need and also explicitly select the AVI DIP and explicitly
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* set its frequency to every VSync. Avoiding to write it twice seems to
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* be enough to solve the problem, but being defensive shouldn't hurt us
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* either. */
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val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
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if (!intel_hdmi->has_hdmi_sink) {
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if (!(val & VIDEO_DIP_ENABLE))
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return;
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val &= ~VIDEO_DIP_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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return;
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}
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switch (intel_dig_port->port) {
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case PORT_B:
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port = VIDEO_DIP_PORT_B;
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break;
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case PORT_C:
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port = VIDEO_DIP_PORT_C;
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break;
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default:
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BUG();
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return;
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}
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if (port != (val & VIDEO_DIP_PORT_MASK)) {
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if (val & VIDEO_DIP_ENABLE) {
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val &= ~VIDEO_DIP_ENABLE;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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val &= ~VIDEO_DIP_PORT_MASK;
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val |= port;
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}
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val |= VIDEO_DIP_ENABLE;
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val &= ~VIDEO_DIP_ENABLE_VENDOR;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
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intel_hdmi_set_spd_infoframe(encoder);
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}
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static void ibx_set_infoframes(struct drm_encoder *encoder,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
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struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
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u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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u32 val = I915_READ(reg);
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u32 port;
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|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
return;
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
return;
|
|
}
|
|
|
|
switch (intel_dig_port->port) {
|
|
case PORT_B:
|
|
port = VIDEO_DIP_PORT_B;
|
|
break;
|
|
case PORT_C:
|
|
port = VIDEO_DIP_PORT_C;
|
|
break;
|
|
case PORT_D:
|
|
port = VIDEO_DIP_PORT_D;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
|
if (val & VIDEO_DIP_ENABLE) {
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
}
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
val |= port;
|
|
}
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void cpt_set_infoframes(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
u32 val = I915_READ(reg);
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
return;
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
return;
|
|
}
|
|
|
|
/* Set both together, unset both together: see the spec. */
|
|
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void vlv_set_infoframes(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
u32 val = I915_READ(reg);
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
return;
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
return;
|
|
}
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void hsw_set_infoframes(struct drm_encoder *encoder,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
|
|
u32 val = I915_READ(reg);
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
I915_WRITE(reg, 0);
|
|
POSTING_READ(reg);
|
|
return;
|
|
}
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
|
|
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
|
|
|
|
I915_WRITE(reg, val);
|
|
POSTING_READ(reg);
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
}
|
|
|
|
static void intel_hdmi_mode_set(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
|
|
u32 hdmi_val;
|
|
|
|
hdmi_val = SDVO_ENCODING_HDMI;
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
hdmi_val |= intel_hdmi->color_range;
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
|
|
|
|
if (crtc->config.pipe_bpp > 24)
|
|
hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
|
|
else
|
|
hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
|
|
|
|
/* Required on CPT */
|
|
if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
|
|
hdmi_val |= HDMI_MODE_SELECT_HDMI;
|
|
|
|
if (intel_hdmi->has_audio) {
|
|
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
|
|
pipe_name(crtc->pipe));
|
|
hdmi_val |= SDVO_AUDIO_ENABLE;
|
|
hdmi_val |= HDMI_MODE_SELECT_HDMI;
|
|
intel_write_eld(&encoder->base, adjusted_mode);
|
|
}
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
|
|
else
|
|
hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
|
|
}
|
|
|
|
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
|
|
enum pipe *pipe)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
u32 tmp;
|
|
|
|
tmp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
if (!(tmp & SDVO_ENABLE))
|
|
return false;
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
*pipe = PORT_TO_PIPE_CPT(tmp);
|
|
else
|
|
*pipe = PORT_TO_PIPE(tmp);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void intel_hdmi_get_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
u32 tmp, flags = 0;
|
|
|
|
tmp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
else
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
else
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
pipe_config->adjusted_mode.flags |= flags;
|
|
}
|
|
|
|
static void intel_enable_hdmi(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
u32 temp;
|
|
u32 enable_bits = SDVO_ENABLE;
|
|
|
|
if (intel_hdmi->has_audio)
|
|
enable_bits |= SDVO_AUDIO_ENABLE;
|
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* HW workaround for IBX, we need to move the port to transcoder A
|
|
* before disabling it, so restore the transcoder select bit here. */
|
|
if (HAS_PCH_IBX(dev))
|
|
enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
|
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
* we do this anyway which shows more stable in testing.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
}
|
|
|
|
temp |= enable_bits;
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
* in first write getting masked.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
}
|
|
}
|
|
|
|
static void vlv_enable_hdmi(struct intel_encoder *encoder)
|
|
{
|
|
}
|
|
|
|
static void intel_disable_hdmi(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
u32 temp;
|
|
u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
|
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* HW workaround for IBX, we need to move the port to transcoder A
|
|
* before disabling it. */
|
|
if (HAS_PCH_IBX(dev)) {
|
|
struct drm_crtc *crtc = encoder->base.crtc;
|
|
int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
|
|
|
|
if (temp & SDVO_PIPE_B_SELECT) {
|
|
temp &= ~SDVO_PIPE_B_SELECT;
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* Again we need to write this twice. */
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* Transcoder selection bits only update
|
|
* effectively on vblank. */
|
|
if (crtc)
|
|
intel_wait_for_vblank(dev, pipe);
|
|
else
|
|
msleep(50);
|
|
}
|
|
}
|
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
* we do this anyway which shows more stable in testing.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
}
|
|
|
|
temp &= ~enable_bits;
|
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
* in first write getting masked.
|
|
*/
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
|
}
|
|
}
|
|
|
|
static int intel_hdmi_mode_valid(struct drm_connector *connector,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
if (mode->clock > 165000)
|
|
return MODE_CLOCK_HIGH;
|
|
if (mode->clock < 20000)
|
|
return MODE_CLOCK_LOW;
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
return MODE_NO_DBLESCAN;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
|
int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
|
|
int desired_bpp;
|
|
|
|
if (intel_hdmi->color_range_auto) {
|
|
/* See CEA-861-E - 5.1 Default Encoding Parameters */
|
|
if (intel_hdmi->has_hdmi_sink &&
|
|
drm_match_cea_mode(adjusted_mode) > 1)
|
|
intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
|
|
else
|
|
intel_hdmi->color_range = 0;
|
|
}
|
|
|
|
if (intel_hdmi->color_range)
|
|
pipe_config->limited_color_range = true;
|
|
|
|
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
|
|
pipe_config->has_pch_encoder = true;
|
|
|
|
/*
|
|
* HDMI is either 12 or 8, so if the display lets 10bpc sneak
|
|
* through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
|
|
* outputs. We also need to check that the higher clock still fits
|
|
* within limits.
|
|
*/
|
|
if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
|
|
&& HAS_PCH_SPLIT(dev)) {
|
|
DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
|
|
desired_bpp = 12*3;
|
|
|
|
/* Need to adjust the port link by 1.5x for 12bpc. */
|
|
pipe_config->port_clock = clock_12bpc;
|
|
} else {
|
|
DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
|
|
desired_bpp = 8*3;
|
|
}
|
|
|
|
if (!pipe_config->bw_constrained) {
|
|
DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
|
|
pipe_config->pipe_bpp = desired_bpp;
|
|
}
|
|
|
|
if (adjusted_mode->clock > 225000) {
|
|
DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static enum drm_connector_status
|
|
intel_hdmi_detect(struct drm_connector *connector, bool force)
|
|
{
|
|
struct drm_device *dev = connector->dev;
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct intel_digital_port *intel_dig_port =
|
|
hdmi_to_dig_port(intel_hdmi);
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct edid *edid;
|
|
enum drm_connector_status status = connector_status_disconnected;
|
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
|
|
connector->base.id, drm_get_connector_name(connector));
|
|
|
|
intel_hdmi->has_hdmi_sink = false;
|
|
intel_hdmi->has_audio = false;
|
|
intel_hdmi->rgb_quant_range_selectable = false;
|
|
edid = drm_get_edid(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
|
|
if (edid) {
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
|
status = connector_status_connected;
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
|
|
intel_hdmi->has_hdmi_sink =
|
|
drm_detect_hdmi_monitor(edid);
|
|
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
|
|
intel_hdmi->rgb_quant_range_selectable =
|
|
drm_rgb_quant_range_selectable(edid);
|
|
}
|
|
kfree(edid);
|
|
}
|
|
|
|
if (status == connector_status_connected) {
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
|
|
intel_hdmi->has_audio =
|
|
(intel_hdmi->force_audio == HDMI_AUDIO_ON);
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static int intel_hdmi_get_modes(struct drm_connector *connector)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
/* We should parse the EDID data and find out if it's an HDMI sink so
|
|
* we can send audio to it.
|
|
*/
|
|
|
|
return intel_ddc_get_modes(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
}
|
|
|
|
static bool
|
|
intel_hdmi_detect_audio(struct drm_connector *connector)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
struct edid *edid;
|
|
bool has_audio = false;
|
|
|
|
edid = drm_get_edid(connector,
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
intel_hdmi->ddc_bus));
|
|
if (edid) {
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL)
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
kfree(edid);
|
|
}
|
|
|
|
return has_audio;
|
|
}
|
|
|
|
static int
|
|
intel_hdmi_set_property(struct drm_connector *connector,
|
|
struct drm_property *property,
|
|
uint64_t val)
|
|
{
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
struct intel_digital_port *intel_dig_port =
|
|
hdmi_to_dig_port(intel_hdmi);
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
int ret;
|
|
|
|
ret = drm_object_property_set_value(&connector->base, property, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (property == dev_priv->force_audio_property) {
|
|
enum hdmi_force_audio i = val;
|
|
bool has_audio;
|
|
|
|
if (i == intel_hdmi->force_audio)
|
|
return 0;
|
|
|
|
intel_hdmi->force_audio = i;
|
|
|
|
if (i == HDMI_AUDIO_AUTO)
|
|
has_audio = intel_hdmi_detect_audio(connector);
|
|
else
|
|
has_audio = (i == HDMI_AUDIO_ON);
|
|
|
|
if (i == HDMI_AUDIO_OFF_DVI)
|
|
intel_hdmi->has_hdmi_sink = 0;
|
|
|
|
intel_hdmi->has_audio = has_audio;
|
|
goto done;
|
|
}
|
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
|
bool old_auto = intel_hdmi->color_range_auto;
|
|
uint32_t old_range = intel_hdmi->color_range;
|
|
|
|
switch (val) {
|
|
case INTEL_BROADCAST_RGB_AUTO:
|
|
intel_hdmi->color_range_auto = true;
|
|
break;
|
|
case INTEL_BROADCAST_RGB_FULL:
|
|
intel_hdmi->color_range_auto = false;
|
|
intel_hdmi->color_range = 0;
|
|
break;
|
|
case INTEL_BROADCAST_RGB_LIMITED:
|
|
intel_hdmi->color_range_auto = false;
|
|
intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (old_auto == intel_hdmi->color_range_auto &&
|
|
old_range == intel_hdmi->color_range)
|
|
return 0;
|
|
|
|
goto done;
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
done:
|
|
if (intel_dig_port->base.base.crtc)
|
|
intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *intel_crtc =
|
|
to_intel_crtc(encoder->base.crtc);
|
|
int port = vlv_dport_to_channel(dport);
|
|
int pipe = intel_crtc->pipe;
|
|
u32 val;
|
|
|
|
if (!IS_VALLEYVIEW(dev))
|
|
return;
|
|
|
|
/* Enable clock channels for this port */
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
|
|
val = 0;
|
|
if (pipe)
|
|
val |= (1<<21);
|
|
else
|
|
val &= ~(1<<21);
|
|
val |= 0x001000c4;
|
|
vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
|
|
|
|
/* HDMI 1.0V-2dB */
|
|
vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
|
|
0x2b245f5f);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
|
|
0x5578b83a);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
|
|
0x0c782040);
|
|
vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
|
|
0x2b247878);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
|
|
0x00002000);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
|
|
DPIO_TX_OCALINIT_EN);
|
|
|
|
/* Program lane clock */
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
|
|
0x00760018);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
|
|
0x00400888);
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
intel_enable_hdmi(encoder);
|
|
|
|
vlv_wait_port_ready(dev_priv, port);
|
|
}
|
|
|
|
static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int port = vlv_dport_to_channel(dport);
|
|
|
|
if (!IS_VALLEYVIEW(dev))
|
|
return;
|
|
|
|
/* Program Tx lane resets to default */
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
|
|
DPIO_PCS_TX_LANE2_RESET |
|
|
DPIO_PCS_TX_LANE1_RESET);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
|
|
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
|
|
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
|
|
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
|
|
DPIO_PCS_CLK_SOFT_RESET);
|
|
|
|
/* Fix up inter-pair skew failure */
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
|
|
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
|
|
0x00002000);
|
|
vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
|
|
DPIO_TX_OCALINIT_EN);
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
}
|
|
|
|
static void intel_hdmi_post_disable(struct intel_encoder *encoder)
|
|
{
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
int port = vlv_dport_to_channel(dport);
|
|
|
|
/* Reset lanes to avoid HDMI flicker (VLV w/a) */
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
|
|
vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
}
|
|
|
|
static void intel_hdmi_destroy(struct drm_connector *connector)
|
|
{
|
|
drm_sysfs_connector_remove(connector);
|
|
drm_connector_cleanup(connector);
|
|
kfree(connector);
|
|
}
|
|
|
|
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
|
|
.dpms = intel_connector_dpms,
|
|
.detect = intel_hdmi_detect,
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
.set_property = intel_hdmi_set_property,
|
|
.destroy = intel_hdmi_destroy,
|
|
};
|
|
|
|
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
|
|
.get_modes = intel_hdmi_get_modes,
|
|
.mode_valid = intel_hdmi_mode_valid,
|
|
.best_encoder = intel_best_encoder,
|
|
};
|
|
|
|
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
|
|
.destroy = intel_encoder_destroy,
|
|
};
|
|
|
|
static void
|
|
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
|
|
{
|
|
intel_attach_force_audio_property(connector);
|
|
intel_attach_broadcast_rgb_property(connector);
|
|
intel_hdmi->color_range_auto = true;
|
|
}
|
|
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
struct intel_connector *intel_connector)
|
|
{
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
enum port port = intel_dig_port->port;
|
|
|
|
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
|
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
|
|
|
|
connector->interlace_allowed = 1;
|
|
connector->doublescan_allowed = 0;
|
|
|
|
switch (port) {
|
|
case PORT_B:
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
|
intel_encoder->hpd_pin = HPD_PORT_B;
|
|
break;
|
|
case PORT_C:
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
|
intel_encoder->hpd_pin = HPD_PORT_C;
|
|
break;
|
|
case PORT_D:
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
|
|
intel_encoder->hpd_pin = HPD_PORT_D;
|
|
break;
|
|
case PORT_A:
|
|
intel_encoder->hpd_pin = HPD_PORT_A;
|
|
/* Internal port only for eDP. */
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
intel_hdmi->write_infoframe = vlv_write_infoframe;
|
|
intel_hdmi->set_infoframes = vlv_set_infoframes;
|
|
} else if (!HAS_PCH_SPLIT(dev)) {
|
|
intel_hdmi->write_infoframe = g4x_write_infoframe;
|
|
intel_hdmi->set_infoframes = g4x_set_infoframes;
|
|
} else if (HAS_DDI(dev)) {
|
|
intel_hdmi->write_infoframe = hsw_write_infoframe;
|
|
intel_hdmi->set_infoframes = hsw_set_infoframes;
|
|
} else if (HAS_PCH_IBX(dev)) {
|
|
intel_hdmi->write_infoframe = ibx_write_infoframe;
|
|
intel_hdmi->set_infoframes = ibx_set_infoframes;
|
|
} else {
|
|
intel_hdmi->write_infoframe = cpt_write_infoframe;
|
|
intel_hdmi->set_infoframes = cpt_set_infoframes;
|
|
}
|
|
|
|
if (HAS_DDI(dev))
|
|
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
|
|
else
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
|
|
|
intel_hdmi_add_properties(intel_hdmi, connector);
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
* generated on the port when a cable is not attached.
|
|
*/
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
}
|
|
}
|
|
|
|
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
|
|
{
|
|
struct intel_digital_port *intel_dig_port;
|
|
struct intel_encoder *intel_encoder;
|
|
struct intel_connector *intel_connector;
|
|
|
|
intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
|
|
if (!intel_dig_port)
|
|
return;
|
|
|
|
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
if (!intel_connector) {
|
|
kfree(intel_dig_port);
|
|
return;
|
|
}
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
intel_encoder->compute_config = intel_hdmi_compute_config;
|
|
intel_encoder->mode_set = intel_hdmi_mode_set;
|
|
intel_encoder->disable = intel_disable_hdmi;
|
|
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
|
|
intel_encoder->get_config = intel_hdmi_get_config;
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
|
|
intel_encoder->pre_enable = intel_hdmi_pre_enable;
|
|
intel_encoder->enable = vlv_enable_hdmi;
|
|
intel_encoder->post_disable = intel_hdmi_post_disable;
|
|
} else {
|
|
intel_encoder->enable = intel_enable_hdmi;
|
|
}
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
intel_encoder->cloneable = false;
|
|
|
|
intel_dig_port->port = port;
|
|
intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
|
|
intel_dig_port->dp.output_reg = 0;
|
|
|
|
intel_hdmi_init_connector(intel_dig_port, intel_connector);
|
|
}
|