0890a26479
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- Support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- Refactoring of ARCompact port to accomodate new ARCv2 ISA
- Miscll updates/cleanups
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Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC architecture updates from Vineet Gupta:
- support for HS38 cores based on ARCv2 ISA
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- refactoring of ARCompact port to accomodate new ARCv2 ISA
- misc updates/cleanups
* tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)
ARC: Fix build failures for ARCompact in linux-next after ARCv2 support
ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support
ARCv2: [vdk] dts files and defconfig for HS38 VDK
ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
ARC: [axs101] Prepare for AXS103
ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores
ARCv2: All bits in place, allow ARCv2 builds
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
ARC: Reduce bitops lines of code using macros
ARCv2: barriers
arch: conditionally define smp_{mb,rmb,wmb}
ARC: add smp barriers around atomics per Documentation/atomic_ops.txt
ARC: add compiler barrier to LLSC based cmpxchg
ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
ARCv2: SMP: clocksource: Enable Global Real Time counter
ARCv2: SMP: ARConnect debug/robustness
ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al
ARC: make plat_smp_ops weak to allow over-rides
ARCv2: clocksource: Introduce 64bit local RTC counter
...
124 lines
2.4 KiB
C
124 lines
2.4 KiB
C
/*
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* Generic barrier definitions, originally based on MN10300 definitions.
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*
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* It should be possible to use these on really simple architectures,
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* but it serves more as a starting point for new ports.
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef __ASM_GENERIC_BARRIER_H
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#define __ASM_GENERIC_BARRIER_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#ifndef nop
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#define nop() asm volatile ("nop")
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#endif
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/*
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* Force strict CPU ordering. And yes, this is required on UP too when we're
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* talking to devices.
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*
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* Fall back to compiler barriers if nothing better is provided.
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*/
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#ifndef mb
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#define mb() barrier()
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#endif
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#ifndef rmb
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#define rmb() mb()
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#endif
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#ifndef wmb
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#define wmb() mb()
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#endif
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#ifndef dma_rmb
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#define dma_rmb() rmb()
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#endif
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#ifndef dma_wmb
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#define dma_wmb() wmb()
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#endif
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#ifndef read_barrier_depends
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#define read_barrier_depends() do { } while (0)
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#endif
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#ifdef CONFIG_SMP
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#ifndef smp_mb
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#define smp_mb() mb()
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#endif
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#ifndef smp_rmb
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#define smp_rmb() rmb()
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#endif
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#ifndef smp_wmb
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#define smp_wmb() wmb()
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#endif
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#ifndef smp_read_barrier_depends
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#define smp_read_barrier_depends() read_barrier_depends()
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#endif
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#else /* !CONFIG_SMP */
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#ifndef smp_mb
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#define smp_mb() barrier()
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#endif
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#ifndef smp_rmb
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#define smp_rmb() barrier()
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#endif
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#ifndef smp_wmb
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#define smp_wmb() barrier()
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#endif
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#ifndef smp_read_barrier_depends
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#define smp_read_barrier_depends() do { } while (0)
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#endif
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#endif /* CONFIG_SMP */
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#ifndef smp_store_mb
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#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); mb(); } while (0)
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#endif
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#ifndef smp_mb__before_atomic
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#define smp_mb__before_atomic() smp_mb()
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#endif
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#ifndef smp_mb__after_atomic
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#define smp_mb__after_atomic() smp_mb()
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#endif
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#endif /* !__ASSEMBLY__ */
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#endif /* __ASM_GENERIC_BARRIER_H */
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