f38ca10a79
Fix all of the remaining OMAP2 PRCM register shift/bitmask macros that did not use the _SHIFT/_MASK suffixes to use them. This makes the use of these macros consistent. It is intended to reduce error, as code can be inspected visually by reviewers to ensure that bitshifts and bitmasks are used in the appropriate places. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
123 lines
2.7 KiB
C
123 lines
2.7 KiB
C
/*
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* OMAP2xxx APLL clock control functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include <plat/prcm.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
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#define EN_APLL_STOPPED 0
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#define EN_APLL_LOCKED 3
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/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
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#define APLLS_CLKIN_19_2MHZ 0
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#define APLLS_CLKIN_13MHZ 2
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#define APLLS_CLKIN_12MHZ 3
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void __iomem *cm_idlest_pll;
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/* Private functions */
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/* Enable an APLL if off */
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static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
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{
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u32 cval, apll_mask;
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apll_mask = EN_APLL_LOCKED << clk->enable_bit;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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if ((cval & apll_mask) == apll_mask)
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return 0; /* apll already enabled */
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cval &= ~apll_mask;
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cval |= apll_mask;
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
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OMAP24XX_CM_IDLEST_VAL, clk->name);
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/*
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* REVISIT: Should we return an error code if omap2_wait_clock_ready()
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* fails?
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*/
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return 0;
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}
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static int omap2_clk_apll96_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);
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}
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static int omap2_clk_apll54_enable(struct clk *clk)
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{
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return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
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}
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/* Stop APLL */
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static void omap2_clk_apll_disable(struct clk *clk)
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{
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u32 cval;
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cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
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cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
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}
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/* Public data */
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const struct clkops clkops_apll96 = {
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.enable = omap2_clk_apll96_enable,
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.disable = omap2_clk_apll_disable,
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};
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const struct clkops clkops_apll54 = {
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.enable = omap2_clk_apll54_enable,
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.disable = omap2_clk_apll_disable,
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};
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/* Public functions */
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u32 omap2xxx_get_apll_clkin(void)
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{
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u32 aplls, srate = 0;
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aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
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aplls &= OMAP24XX_APLLS_CLKIN_MASK;
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aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
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if (aplls == APLLS_CLKIN_19_2MHZ)
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srate = 19200000;
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else if (aplls == APLLS_CLKIN_13MHZ)
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srate = 13000000;
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else if (aplls == APLLS_CLKIN_12MHZ)
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srate = 12000000;
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return srate;
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}
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