![Andreas Herrmann](/assets/img/avatar_default.png)
Exit early when there's no support for a particular CPU family. Also, fixup the "no support for this CPU vendor" to be issued only when the driver is attempted to be loaded on an unsupported vendor. Cc: stable@vger.kernel.org Cc: Tigran Aivazian <tigran@aivazian.fsnet.co.uk> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: http://lkml.kernel.org/r/20120411163849.GE4794@alberich.amd.com [Boris: add a commit msg because Andreas is lazy] Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
396 lines
8.8 KiB
C
396 lines
8.8 KiB
C
/*
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* AMD CPU Microcode Update Driver for Linux
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* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
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*
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* Author: Peter Oruba <peter.oruba@amd.com>
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*
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* Based on work by:
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* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
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*
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* Maintainers:
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* Andreas Herrmann <andreas.herrmann3@amd.com>
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* Borislav Petkov <borislav.petkov@amd.com>
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*
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* This driver allows to upgrade microcode on F10h AMD
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* CPUs and later.
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*
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* Licensed under the terms of the GNU General Public
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* License version 2. See file COPYING for details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/firmware.h>
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#include <linux/pci_ids.h>
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#include <linux/uaccess.h>
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#include <linux/vmalloc.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/microcode.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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MODULE_DESCRIPTION("AMD Microcode Update Driver");
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MODULE_AUTHOR("Peter Oruba");
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MODULE_LICENSE("GPL v2");
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#define UCODE_MAGIC 0x00414d44
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#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
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#define UCODE_UCODE_TYPE 0x00000001
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struct equiv_cpu_entry {
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u32 installed_cpu;
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u32 fixed_errata_mask;
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u32 fixed_errata_compare;
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u16 equiv_cpu;
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u16 res;
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} __attribute__((packed));
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struct microcode_header_amd {
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u32 data_code;
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u32 patch_id;
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u16 mc_patch_data_id;
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u8 mc_patch_data_len;
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u8 init_flag;
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u32 mc_patch_data_checksum;
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u32 nb_dev_id;
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u32 sb_dev_id;
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u16 processor_rev_id;
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u8 nb_rev_id;
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u8 sb_rev_id;
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u8 bios_api_rev;
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u8 reserved1[3];
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u32 match_reg[8];
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} __attribute__((packed));
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struct microcode_amd {
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struct microcode_header_amd hdr;
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unsigned int mpb[0];
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};
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#define SECTION_HDR_SIZE 8
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#define CONTAINER_HDR_SZ 12
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static struct equiv_cpu_entry *equiv_cpu_table;
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/* page-sized ucode patch buffer */
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void *patch;
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static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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csig->rev = c->microcode;
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pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
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return 0;
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}
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static unsigned int verify_ucode_size(int cpu, u32 patch_size,
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unsigned int size)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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u32 max_size;
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#define F1XH_MPB_MAX_SIZE 2048
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#define F14H_MPB_MAX_SIZE 1824
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#define F15H_MPB_MAX_SIZE 4096
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switch (c->x86) {
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case 0x14:
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max_size = F14H_MPB_MAX_SIZE;
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break;
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case 0x15:
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max_size = F15H_MPB_MAX_SIZE;
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break;
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default:
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max_size = F1XH_MPB_MAX_SIZE;
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break;
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}
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if (patch_size > min_t(u32, size, max_size)) {
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pr_err("patch size mismatch\n");
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return 0;
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}
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return patch_size;
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}
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static u16 find_equiv_id(void)
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{
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unsigned int current_cpu_id, i = 0;
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BUG_ON(equiv_cpu_table == NULL);
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current_cpu_id = cpuid_eax(0x00000001);
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while (equiv_cpu_table[i].installed_cpu != 0) {
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if (current_cpu_id == equiv_cpu_table[i].installed_cpu)
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return equiv_cpu_table[i].equiv_cpu;
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i++;
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}
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return 0;
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}
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/*
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* we signal a good patch is found by returning its size > 0
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*/
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static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
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unsigned int leftover_size, int rev,
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unsigned int *current_size)
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{
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struct microcode_header_amd *mc_hdr;
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unsigned int actual_size;
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u16 equiv_cpu_id;
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/* size of the current patch we're staring at */
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*current_size = *(u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE;
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equiv_cpu_id = find_equiv_id();
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if (!equiv_cpu_id)
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return 0;
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/*
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* let's look at the patch header itself now
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*/
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mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE);
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if (mc_hdr->processor_rev_id != equiv_cpu_id)
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return 0;
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/* ucode might be chipset specific -- currently we don't support this */
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if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
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pr_err("CPU%d: chipset specific code not yet supported\n",
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cpu);
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return 0;
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}
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if (mc_hdr->patch_id <= rev)
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return 0;
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/*
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* now that the header looks sane, verify its size
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*/
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actual_size = verify_ucode_size(cpu, *current_size, leftover_size);
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if (!actual_size)
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return 0;
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/* clear the patch buffer */
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memset(patch, 0, PAGE_SIZE);
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/* all looks ok, get the binary patch */
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get_ucode_data(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size);
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return actual_size;
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}
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static int apply_microcode_amd(int cpu)
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{
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u32 rev, dummy;
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int cpu_num = raw_smp_processor_id();
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
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struct microcode_amd *mc_amd = uci->mc;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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/* We should bind the task to the CPU */
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BUG_ON(cpu_num != cpu);
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if (mc_amd == NULL)
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return 0;
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wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
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/* get patch id after patching */
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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/* check current patch id and patch's id for match */
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if (rev != mc_amd->hdr.patch_id) {
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pr_err("CPU%d: update failed for patch_level=0x%08x\n",
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cpu, mc_amd->hdr.patch_id);
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return -1;
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}
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pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
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uci->cpu_sig.rev = rev;
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c->microcode = rev;
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return 0;
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}
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static int install_equiv_cpu_table(const u8 *buf)
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{
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unsigned int *ibuf = (unsigned int *)buf;
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unsigned int type = ibuf[1];
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unsigned int size = ibuf[2];
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if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
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pr_err("empty section/"
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"invalid type field in container file section header\n");
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return -EINVAL;
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}
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equiv_cpu_table = vmalloc(size);
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if (!equiv_cpu_table) {
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pr_err("failed to allocate equivalent CPU table\n");
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return -ENOMEM;
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}
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get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
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/* add header length */
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return size + CONTAINER_HDR_SZ;
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}
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static void free_equiv_cpu_table(void)
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{
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vfree(equiv_cpu_table);
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equiv_cpu_table = NULL;
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}
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static enum ucode_state
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generic_load_microcode(int cpu, const u8 *data, size_t size)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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struct microcode_header_amd *mc_hdr = NULL;
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unsigned int mc_size, leftover, current_size = 0;
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int offset;
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const u8 *ucode_ptr = data;
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void *new_mc = NULL;
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unsigned int new_rev = uci->cpu_sig.rev;
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enum ucode_state state = UCODE_ERROR;
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offset = install_equiv_cpu_table(ucode_ptr);
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if (offset < 0) {
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pr_err("failed to create equivalent cpu table\n");
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goto out;
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}
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ucode_ptr += offset;
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leftover = size - offset;
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if (*(u32 *)ucode_ptr != UCODE_UCODE_TYPE) {
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pr_err("invalid type field in container file section header\n");
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goto free_table;
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}
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while (leftover) {
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mc_size = get_matching_microcode(cpu, ucode_ptr, leftover,
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new_rev, ¤t_size);
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if (mc_size) {
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mc_hdr = patch;
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new_mc = patch;
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new_rev = mc_hdr->patch_id;
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goto out_ok;
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}
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ucode_ptr += current_size;
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leftover -= current_size;
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}
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if (!new_mc) {
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state = UCODE_NFOUND;
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goto free_table;
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}
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out_ok:
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uci->mc = new_mc;
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state = UCODE_OK;
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pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
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cpu, uci->cpu_sig.rev, new_rev);
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free_table:
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free_equiv_cpu_table();
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out:
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return state;
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}
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/*
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* AMD microcode firmware naming convention, up to family 15h they are in
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* the legacy file:
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*
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* amd-ucode/microcode_amd.bin
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*
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* This legacy file is always smaller than 2K in size.
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*
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* Starting at family 15h they are in family specific firmware files:
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*
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* amd-ucode/microcode_amd_fam15h.bin
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* amd-ucode/microcode_amd_fam16h.bin
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* ...
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*
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* These might be larger than 2K.
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*/
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static enum ucode_state request_microcode_amd(int cpu, struct device *device)
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{
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char fw_name[36] = "amd-ucode/microcode_amd.bin";
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const struct firmware *fw;
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enum ucode_state ret = UCODE_NFOUND;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if (c->x86 >= 0x15)
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snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
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if (request_firmware(&fw, (const char *)fw_name, device)) {
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pr_err("failed to load file %s\n", fw_name);
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goto out;
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}
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ret = UCODE_ERROR;
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if (*(u32 *)fw->data != UCODE_MAGIC) {
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pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
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goto fw_release;
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}
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ret = generic_load_microcode(cpu, fw->data, fw->size);
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fw_release:
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release_firmware(fw);
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out:
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return ret;
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}
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static enum ucode_state
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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{
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return UCODE_ERROR;
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}
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static void microcode_fini_cpu_amd(int cpu)
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{
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struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
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uci->mc = NULL;
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}
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static struct microcode_ops microcode_amd_ops = {
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.request_microcode_user = request_microcode_user,
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.request_microcode_fw = request_microcode_amd,
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.collect_cpu_info = collect_cpu_info_amd,
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.apply_microcode = apply_microcode_amd,
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.microcode_fini_cpu = microcode_fini_cpu_amd,
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};
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struct microcode_ops * __init init_amd_microcode(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
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pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
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return NULL;
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}
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patch = (void *)get_zeroed_page(GFP_KERNEL);
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if (!patch)
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return NULL;
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return µcode_amd_ops;
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}
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void __exit exit_amd_microcode(void)
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{
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free_page((unsigned long)patch);
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}
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