![Paul Gortmaker](/assets/img/avatar_default.png)
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0
("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/blackfin uses of the __cpuinit macros from
all C files. Currently blackfin does not have any __CPUINIT used in
assembly files.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Bob Liu <lliubbo@gmail.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: uclinux-dist-devel@blackfin.uclinux.org
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
500 lines
12 KiB
C
500 lines
12 KiB
C
/*
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* Blackfin performance counters
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Ripped from SuperH version:
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*
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* Copyright (C) 2009 Paul Mundt
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*
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* Heavily based on the x86 and PowerPC implementations.
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*
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* x86:
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* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
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* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
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* Copyright (C) 2009 Jaswinder Singh Rajput
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* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
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* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
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* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
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*
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* ppc:
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/perf_event.h>
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#include <asm/bfin_pfmon.h>
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/*
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* We have two counters, and each counter can support an event type.
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* The 'o' is PFCNTx=1 and 's' is PFCNTx=0
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*
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* 0x04 o pc invariant branches
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* 0x06 o mispredicted branches
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* 0x09 o predicted branches taken
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* 0x0B o EXCPT insn
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* 0x0C o CSYNC/SSYNC insn
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* 0x0D o Insns committed
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* 0x0E o Interrupts taken
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* 0x0F o Misaligned address exceptions
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* 0x80 o Code memory fetches stalled due to DMA
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* 0x83 o 64bit insn fetches delivered
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* 0x9A o data cache fills (bank a)
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* 0x9B o data cache fills (bank b)
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* 0x9C o data cache lines evicted (bank a)
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* 0x9D o data cache lines evicted (bank b)
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* 0x9E o data cache high priority fills
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* 0x9F o data cache low priority fills
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* 0x00 s loop 0 iterations
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* 0x01 s loop 1 iterations
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* 0x0A s CSYNC/SSYNC stalls
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* 0x10 s DAG read/after write hazards
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* 0x13 s RAW data hazards
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* 0x81 s code TAG stalls
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* 0x82 s code fill stalls
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* 0x90 s processor to memory stalls
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* 0x91 s data memory stalls not hidden by 0x90
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* 0x92 s data store buffer full stalls
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* 0x93 s data memory write buffer full stalls due to high->low priority
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* 0x95 s data memory fill buffer stalls
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* 0x96 s data TAG collision stalls
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* 0x97 s data collision stalls
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* 0x98 s data stalls
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* 0x99 s data stalls sent to processor
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*/
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static const int event_map[] = {
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/* use CYCLES cpu register */
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[PERF_COUNT_HW_CPU_CYCLES] = -1,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
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[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x83,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
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[PERF_COUNT_HW_BUS_CYCLES] = -1,
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};
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#define C(x) PERF_COUNT_HW_CACHE_##x
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static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[C(L1D)] = { /* Data bank A */
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS) ] = 0x9A,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS) ] = 0,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS) ] = 0,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS) ] = 0x83,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = 0,
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[C(RESULT_MISS) ] = 0,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = -1,
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[C(RESULT_MISS) ] = -1,
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},
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},
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};
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const char *perf_pmu_name(void)
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{
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return "bfin";
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}
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EXPORT_SYMBOL(perf_pmu_name);
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int perf_num_counters(void)
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{
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return ARRAY_SIZE(event_map);
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}
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EXPORT_SYMBOL(perf_num_counters);
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static u64 bfin_pfmon_read(int idx)
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{
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return bfin_read32(PFCNTR0 + (idx * 4));
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}
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static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
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{
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bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
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}
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static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
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{
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u32 val, mask;
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val = PFPWR;
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if (idx) {
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mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
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/* The packed config is for event0, so shift it to event1 slots */
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val |= (hwc->config << (PFMON1_P - PFMON0_P));
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val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
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bfin_write_PFCNTR1(0);
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} else {
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mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
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val |= hwc->config;
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bfin_write_PFCNTR0(0);
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}
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bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
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}
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static void bfin_pfmon_disable_all(void)
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{
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bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
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}
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static void bfin_pfmon_enable_all(void)
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{
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bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
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}
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struct cpu_hw_events {
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struct perf_event *events[MAX_HWEVENTS];
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unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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};
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
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static int hw_perf_cache_event(int config, int *evp)
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{
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unsigned long type, op, result;
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int ev;
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/* unpack config */
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type = config & 0xff;
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op = (config >> 8) & 0xff;
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result = (config >> 16) & 0xff;
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if (type >= PERF_COUNT_HW_CACHE_MAX ||
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op >= PERF_COUNT_HW_CACHE_OP_MAX ||
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result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ev = cache_events[type][op][result];
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if (ev == 0)
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return -EOPNOTSUPP;
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if (ev == -1)
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return -EINVAL;
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*evp = ev;
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return 0;
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}
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static void bfin_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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int shift = 0;
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/*
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* Depending on the counter configuration, they may or may not
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* be chained, in which case the previous counter value can be
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* updated underneath us if the lower-half overflows.
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*
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* Our tactic to handle this is to first atomically read and
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* exchange a new raw count - then add that new-prev delta
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* count to the generic counter atomically.
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*
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* As there is no interrupt associated with the overflow events,
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* this is the simplest approach for maintaining consistency.
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*/
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = bfin_pfmon_read(idx);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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/*
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* Now we have the new raw value and have updated the prev
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* timestamp already. We can now calculate the elapsed delta
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* (counter-)time and add that to the generic counter.
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*
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* Careful, not all hw sign-extends above the physical width
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* of the count.
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*/
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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}
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static void bfin_pmu_stop(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (!(event->hw.state & PERF_HES_STOPPED)) {
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bfin_pfmon_disable(hwc, idx);
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cpuc->events[idx] = NULL;
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event->hw.state |= PERF_HES_STOPPED;
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}
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if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
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bfin_perf_event_update(event, &event->hw, idx);
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event->hw.state |= PERF_HES_UPTODATE;
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}
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}
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static void bfin_pmu_start(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
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cpuc->events[idx] = event;
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event->hw.state = 0;
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bfin_pfmon_enable(hwc, idx);
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}
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static void bfin_pmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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bfin_pmu_stop(event, PERF_EF_UPDATE);
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__clear_bit(event->hw.idx, cpuc->used_mask);
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perf_event_update_userpage(event);
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}
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static int bfin_pmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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int ret = -EAGAIN;
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perf_pmu_disable(event->pmu);
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if (__test_and_set_bit(idx, cpuc->used_mask)) {
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idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
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if (idx == MAX_HWEVENTS)
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goto out;
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__set_bit(idx, cpuc->used_mask);
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hwc->idx = idx;
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}
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bfin_pfmon_disable(hwc, idx);
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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bfin_pmu_start(event, PERF_EF_RELOAD);
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perf_event_update_userpage(event);
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ret = 0;
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out:
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perf_pmu_enable(event->pmu);
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return ret;
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}
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static void bfin_pmu_read(struct perf_event *event)
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{
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bfin_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int bfin_pmu_event_init(struct perf_event *event)
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{
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struct perf_event_attr *attr = &event->attr;
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struct hw_perf_event *hwc = &event->hw;
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int config = -1;
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int ret;
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if (attr->exclude_hv || attr->exclude_idle)
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return -EPERM;
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/*
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* All of the on-chip counters are "limited", in that they have
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* no interrupts, and are therefore unable to do sampling without
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* further work and timer assistance.
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*/
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if (hwc->sample_period)
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return -EINVAL;
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ret = 0;
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switch (attr->type) {
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case PERF_TYPE_RAW:
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config = PFMON(0, attr->config & PFMON_MASK) |
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PFCNT(0, !(attr->config & 0x100));
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break;
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case PERF_TYPE_HW_CACHE:
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ret = hw_perf_cache_event(attr->config, &config);
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break;
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case PERF_TYPE_HARDWARE:
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if (attr->config >= ARRAY_SIZE(event_map))
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return -EINVAL;
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config = event_map[attr->config];
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break;
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}
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if (config == -1)
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return -EINVAL;
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if (!attr->exclude_kernel)
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config |= PFCEN(0, PFCEN_ENABLE_SUPV);
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if (!attr->exclude_user)
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config |= PFCEN(0, PFCEN_ENABLE_USER);
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hwc->config |= config;
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return ret;
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}
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static void bfin_pmu_enable(struct pmu *pmu)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct perf_event *event;
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struct hw_perf_event *hwc;
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int i;
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for (i = 0; i < MAX_HWEVENTS; ++i) {
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event = cpuc->events[i];
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if (!event)
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continue;
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hwc = &event->hw;
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bfin_pfmon_enable(hwc, hwc->idx);
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}
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bfin_pfmon_enable_all();
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}
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static void bfin_pmu_disable(struct pmu *pmu)
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{
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bfin_pfmon_disable_all();
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}
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static struct pmu pmu = {
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.pmu_enable = bfin_pmu_enable,
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.pmu_disable = bfin_pmu_disable,
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.event_init = bfin_pmu_event_init,
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.add = bfin_pmu_add,
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.del = bfin_pmu_del,
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.start = bfin_pmu_start,
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.stop = bfin_pmu_stop,
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.read = bfin_pmu_read,
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};
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static void bfin_pmu_setup(int cpu)
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{
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struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
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memset(cpuhw, 0, sizeof(struct cpu_hw_events));
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}
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static int
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bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
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{
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unsigned int cpu = (long)hcpu;
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switch (action & ~CPU_TASKS_FROZEN) {
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case CPU_UP_PREPARE:
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bfin_write_PFCTL(0);
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bfin_pmu_setup(cpu);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static int __init bfin_pmu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
|
|
if (!ret)
|
|
perf_cpu_notifier(bfin_pmu_notifier);
|
|
|
|
return ret;
|
|
}
|
|
early_initcall(bfin_pmu_init);
|