![Stephen Boyd](/assets/img/avatar_default.png)
It seems that this assignment is done twice in a row. Remove the duplicate assignment. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Steven Miao <realmz6@gmail.com> Cc: trivial@kernel.org Signed-off-by: Bob Liu <lliubbo@gmail.com>
393 lines
9.3 KiB
C
393 lines
9.3 KiB
C
/*
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* Based on arm clockevents implementation and old bfin time tick.
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*
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* Copyright 2008-2009 Analog Devics Inc.
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* 2008 GeoTechnologies
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* Vitja Makarov
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*
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* Licensed under the GPL-2
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*/
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#include <linux/module.h>
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#include <linux/profile.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/cpufreq.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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#include <asm/gptimers.h>
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#include <asm/nmi.h>
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
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{
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#ifdef CONFIG_CPU_FREQ
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return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
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#else
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return get_cycles();
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#endif
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}
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static struct clocksource bfin_cs_cycles = {
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.name = "bfin_cs_cycles",
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.rating = 400,
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.read = bfin_read_cycles,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static inline unsigned long long bfin_cs_cycles_sched_clock(void)
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{
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return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
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bfin_cs_cycles.mult, bfin_cs_cycles.shift);
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}
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static int __init bfin_cs_cycles_init(void)
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{
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if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
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panic("failed to register clocksource");
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return 0;
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}
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#else
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# define bfin_cs_cycles_init()
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#endif
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#ifdef CONFIG_GPTMR0_CLOCKSOURCE
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void __init setup_gptimer0(void)
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{
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disable_gptimers(TIMER0bit);
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#ifdef CONFIG_BF60x
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bfin_write16(TIMER_DATA_IMSK, 0);
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set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
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| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
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#else
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
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#endif
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set_gptimer_period(TIMER0_id, -1);
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set_gptimer_pwidth(TIMER0_id, -2);
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SSYNC();
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enable_gptimers(TIMER0bit);
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}
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static cycle_t bfin_read_gptimer0(struct clocksource *cs)
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{
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return bfin_read_TIMER0_COUNTER();
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}
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static struct clocksource bfin_cs_gptimer0 = {
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.name = "bfin_cs_gptimer0",
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.rating = 350,
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.read = bfin_read_gptimer0,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
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{
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return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
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bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
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}
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static int __init bfin_cs_gptimer0_init(void)
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{
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setup_gptimer0();
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if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
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panic("failed to register clocksource");
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return 0;
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}
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#else
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# define bfin_cs_gptimer0_init()
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#endif
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#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
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/* prefer to use cycles since it has higher rating */
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notrace unsigned long long sched_clock(void)
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{
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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return bfin_cs_cycles_sched_clock();
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#else
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return bfin_cs_gptimer0_sched_clock();
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#endif
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}
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#endif
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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static int bfin_gptmr0_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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disable_gptimers(TIMER0bit);
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/* it starts counting three SCLK cycles after the TIMENx bit is set */
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set_gptimer_pwidth(TIMER0_id, cycles - 3);
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enable_gptimers(TIMER0bit);
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return 0;
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}
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static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC: {
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#ifndef CONFIG_BF60x
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_IRQ_ENA | \
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TIMER_PERIOD_CNT | TIMER_MODE_PWM);
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#else
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set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
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| TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
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#endif
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set_gptimer_period(TIMER0_id, get_sclk() / HZ);
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set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
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enable_gptimers(TIMER0bit);
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break;
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}
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case CLOCK_EVT_MODE_ONESHOT:
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disable_gptimers(TIMER0bit);
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#ifndef CONFIG_BF60x
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set_gptimer_config(TIMER0_id, \
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TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
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#else
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set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
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| TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
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#endif
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set_gptimer_period(TIMER0_id, 0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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disable_gptimers(TIMER0bit);
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static void bfin_gptmr0_ack(void)
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{
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clear_gptimer_intr(TIMER0_id);
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}
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static void __init bfin_gptmr0_init(void)
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{
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disable_gptimers(TIMER0bit);
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}
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#ifdef CONFIG_CORE_TIMER_IRQ_L1
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__attribute__((l1_text))
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#endif
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irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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smp_mb();
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/*
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* We want to ACK before we handle so that we can handle smaller timer
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* intervals. This way if the timer expires again while we're handling
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* things, we're more likely to see that 2nd int rather than swallowing
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* it by ACKing the int at the end of this handler.
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*/
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bfin_gptmr0_ack();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction gptmr0_irq = {
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.name = "Blackfin GPTimer0",
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.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
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.handler = bfin_gptmr0_interrupt,
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};
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static struct clock_event_device clockevent_gptmr0 = {
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.name = "bfin_gptimer0",
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.rating = 300,
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.irq = IRQ_TIMER0,
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.shift = 32,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = bfin_gptmr0_set_next_event,
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.set_mode = bfin_gptmr0_set_mode,
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};
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static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
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{
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unsigned long clock_tick;
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clock_tick = get_sclk();
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evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(-1, evt);
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evt->min_delta_ns = clockevent_delta2ns(100, evt);
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evt->cpumask = cpumask_of(0);
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clockevents_register_device(evt);
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}
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#endif /* CONFIG_TICKSOURCE_GPTMR0 */
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#if defined(CONFIG_TICKSOURCE_CORETMR)
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/* per-cpu local core timer */
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DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
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static int bfin_coretmr_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TCOUNT(cycles);
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CSYNC();
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bfin_write_TCNTL(TMPWR | TMREN);
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return 0;
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}
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static void bfin_coretmr_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC: {
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unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(tcount);
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bfin_write_TCOUNT(tcount);
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CSYNC();
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bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
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break;
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}
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case CLOCK_EVT_MODE_ONESHOT:
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(0);
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bfin_write_TCOUNT(0);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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bfin_write_TCNTL(0);
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CSYNC();
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break;
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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void bfin_coretmr_init(void)
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{
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/* power up the timer, but don't enable it just yet */
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bfin_write_TCNTL(TMPWR);
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CSYNC();
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/* the TSCALE prescaler counter. */
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bfin_write_TSCALE(TIME_SCALE - 1);
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bfin_write_TPERIOD(0);
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bfin_write_TCOUNT(0);
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CSYNC();
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}
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#ifdef CONFIG_CORE_TIMER_IRQ_L1
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__attribute__((l1_text))
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#endif
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irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
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smp_mb();
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evt->event_handler(evt);
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touch_nmi_watchdog();
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return IRQ_HANDLED;
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}
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static struct irqaction coretmr_irq = {
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.name = "Blackfin CoreTimer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
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.handler = bfin_coretmr_interrupt,
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};
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void bfin_coretmr_clockevent_init(void)
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{
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unsigned long clock_tick;
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
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#ifdef CONFIG_SMP
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evt->broadcast = smp_timer_broadcast;
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#endif
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evt->name = "bfin_core_timer";
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evt->rating = 350;
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evt->irq = -1;
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evt->shift = 32;
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evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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evt->set_next_event = bfin_coretmr_set_next_event;
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evt->set_mode = bfin_coretmr_set_mode;
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clock_tick = get_cclk() / TIME_SCALE;
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evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(-1, evt);
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evt->min_delta_ns = clockevent_delta2ns(100, evt);
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evt->cpumask = cpumask_of(cpu);
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clockevents_register_device(evt);
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}
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#endif /* CONFIG_TICKSOURCE_CORETMR */
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void read_persistent_clock(struct timespec *ts)
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{
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time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
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ts->tv_sec = secs_since_1970;
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ts->tv_nsec = 0;
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}
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void __init time_init(void)
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{
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#ifdef CONFIG_RTC_DRV_BFIN
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/* [#2663] hack to filter junk RTC values that would cause
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* userspace to have to deal with time values greater than
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* 2^31 seconds (which uClibc cannot cope with yet)
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*/
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if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
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printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
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bfin_write_RTC_STAT(0);
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}
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#endif
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bfin_cs_cycles_init();
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bfin_cs_gptimer0_init();
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#if defined(CONFIG_TICKSOURCE_CORETMR)
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bfin_coretmr_init();
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setup_irq(IRQ_CORETMR, &coretmr_irq);
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bfin_coretmr_clockevent_init();
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#endif
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#if defined(CONFIG_TICKSOURCE_GPTMR0)
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bfin_gptmr0_init();
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setup_irq(IRQ_TIMER0, &gptmr0_irq);
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gptmr0_irq.dev_id = &clockevent_gptmr0;
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bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
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#endif
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#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
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# error at least one clock event device is required
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#endif
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}
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