319bbe0ef5
improve the common clock support code for MPC512x - expand the CCM register set declaration with MPC5125 related registers (which reside in the previously "reserved" area) - tell the MPC5121, MPC5123, and MPC5125 SoC variants apart, and derive the availability of components and their clocks from the detected SoC (MBX, AXE, VIU, SPDIF, PATA, SATA, PCI, second FEC, second SDHC, number of PSC components, type of NAND flash controller, interpretation of the CPMF bitfield, PSC/CAN mux0 stage input clocks, output clocks on SoC pins) - add backwards compatibility (allow operation against a device tree which lacks clock related specs) for MPC5125 FECs, too telling SoC variants apart and adjusting the clock tree's generation occurs at runtime, a common generic binary supports all of the chips the MPC5125 approach to the NFC clock (one register with two counters for the high and low periods of the clock) is not implemented, as there are no users and there is no common implementation which supports this kind of clock -- the new implementation would be unused and could not get verified, so it shall wait until there is demand Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/*
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* This header provides constants for MPC512x clock specs in DT bindings.
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*/
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#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
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#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
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#define MPC512x_CLK_DUMMY 0
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#define MPC512x_CLK_REF 1
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#define MPC512x_CLK_SYS 2
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#define MPC512x_CLK_DIU 3
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#define MPC512x_CLK_VIU 4
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#define MPC512x_CLK_CSB 5
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#define MPC512x_CLK_E300 6
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#define MPC512x_CLK_IPS 7
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#define MPC512x_CLK_FEC 8
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#define MPC512x_CLK_SATA 9
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#define MPC512x_CLK_PATA 10
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#define MPC512x_CLK_NFC 11
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#define MPC512x_CLK_LPC 12
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#define MPC512x_CLK_MBX_BUS 13
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#define MPC512x_CLK_MBX 14
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#define MPC512x_CLK_MBX_3D 15
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#define MPC512x_CLK_AXE 16
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#define MPC512x_CLK_USB1 17
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#define MPC512x_CLK_USB2 18
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#define MPC512x_CLK_I2C 19
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#define MPC512x_CLK_MSCAN0_MCLK 20
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#define MPC512x_CLK_MSCAN1_MCLK 21
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#define MPC512x_CLK_MSCAN2_MCLK 22
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#define MPC512x_CLK_MSCAN3_MCLK 23
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#define MPC512x_CLK_BDLC 24
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#define MPC512x_CLK_SDHC 25
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#define MPC512x_CLK_PCI 26
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#define MPC512x_CLK_PSC_MCLK_IN 27
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#define MPC512x_CLK_SPDIF_TX 28
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#define MPC512x_CLK_SPDIF_RX 29
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#define MPC512x_CLK_SPDIF_MCLK 30
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#define MPC512x_CLK_SPDIF 31
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#define MPC512x_CLK_AC97 32
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#define MPC512x_CLK_PSC0_MCLK 33
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#define MPC512x_CLK_PSC1_MCLK 34
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#define MPC512x_CLK_PSC2_MCLK 35
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#define MPC512x_CLK_PSC3_MCLK 36
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#define MPC512x_CLK_PSC4_MCLK 37
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#define MPC512x_CLK_PSC5_MCLK 38
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#define MPC512x_CLK_PSC6_MCLK 39
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#define MPC512x_CLK_PSC7_MCLK 40
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#define MPC512x_CLK_PSC8_MCLK 41
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#define MPC512x_CLK_PSC9_MCLK 42
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#define MPC512x_CLK_PSC10_MCLK 43
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#define MPC512x_CLK_PSC11_MCLK 44
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#define MPC512x_CLK_PSC_FIFO 45
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#define MPC512x_CLK_PSC0 46
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#define MPC512x_CLK_PSC1 47
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#define MPC512x_CLK_PSC2 48
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#define MPC512x_CLK_PSC3 49
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#define MPC512x_CLK_PSC4 50
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#define MPC512x_CLK_PSC5 51
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#define MPC512x_CLK_PSC6 52
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#define MPC512x_CLK_PSC7 53
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#define MPC512x_CLK_PSC8 54
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#define MPC512x_CLK_PSC9 55
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#define MPC512x_CLK_PSC10 56
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#define MPC512x_CLK_PSC11 57
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#define MPC512x_CLK_SDHC2 58
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#define MPC512x_CLK_FEC2 59
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#define MPC512x_CLK_OUT0_CLK 60
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#define MPC512x_CLK_OUT1_CLK 61
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#define MPC512x_CLK_OUT2_CLK 62
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#define MPC512x_CLK_OUT3_CLK 63
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#define MPC512x_CLK_CAN_CLK_IN 64
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#define MPC512x_CLK_LAST_PUBLIC 64
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#endif
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