![Tony Luck](/assets/img/avatar_default.png)
Back 2010 during a revamp of the irq code some initializations
were moved from ia64_mca_init() to ia64_mca_late_init() in
commit c75f2aa13f
Cannot use register_percpu_irq() from ia64_mca_init()
But this was hideously wrong. First of all these initializations
are now down far too late. Specifically after all the other cpus
have been brought up and initialized their own CMC vectors from
smp_callin(). Also ia64_mca_late_init() may be called from any cpu
so the line:
ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
is generally not executed on the BSP, and so the CMC vector isn't
setup at all on that processor.
Make use of the arch_early_irq_init() hook to get this code executed
at just the right moment: not too early, not too late.
Reported-by: Fred Hartnett <fred.hartnett@hp.com>
Tested-by: Fred Hartnett <fred.hartnett@hp.com>
Cc: stable@kernel.org # v2.6.37+
Signed-off-by: Tony Luck <tony.luck@intel.com>
203 lines
4.7 KiB
C
203 lines
4.7 KiB
C
/*
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* linux/arch/ia64/kernel/irq.c
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*
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* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
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*
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* This file contains the code used by various IRQ handling routines:
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* asking for different IRQs should be done through these routines
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* instead of just grabbing them. Thus setups with different IRQ numbers
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* shouldn't result in any weird surprises, and installing new handlers
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* should be easier.
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*
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* Copyright (C) Ashok Raj<ashok.raj@intel.com>, Intel Corporation 2004
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*
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* 4/14/2004: Added code to handle cpu migration and do safe irq
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* migration without losing interrupts for iosapic
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* architecture.
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*/
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#include <asm/delay.h>
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#include <asm/uaccess.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <asm/mca.h>
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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printk(KERN_ERR "Unexpected irq vector 0x%x on CPU %u!\n", irq, smp_processor_id());
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}
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#ifdef CONFIG_IA64_GENERIC
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ia64_vector __ia64_irq_to_vector(int irq)
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{
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return irq_cfg[irq].vector;
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}
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unsigned int __ia64_local_vector_to_irq (ia64_vector vec)
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{
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return __get_cpu_var(vector_irq)[vec];
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}
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#endif
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/*
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* Interrupt statistics:
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*/
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atomic_t irq_err_count;
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/*
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* /proc/interrupts printing:
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*/
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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return 0;
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}
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#ifdef CONFIG_SMP
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static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
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void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
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{
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if (irq < NR_IRQS) {
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cpumask_copy(irq_get_irq_data(irq)->affinity,
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cpumask_of(cpu_logical_id(hwid)));
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irq_redir[irq] = (char) (redir & 0xff);
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}
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}
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bool is_affinity_mask_valid(const struct cpumask *cpumask)
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{
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if (ia64_platform_is("sn2")) {
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/* Only allow one CPU to be specified in the smp_affinity mask */
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if (cpumask_weight(cpumask) != 1)
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return false;
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}
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return true;
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}
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#endif /* CONFIG_SMP */
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int __init arch_early_irq_init(void)
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{
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ia64_mca_irq_init();
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return 0;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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unsigned int vectors_in_migration[NR_IRQS];
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/*
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* Since cpu_online_mask is already updated, we just need to check for
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* affinity that has zeros
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*/
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static void migrate_irqs(void)
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{
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int irq, new_cpu;
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for (irq=0; irq < NR_IRQS; irq++) {
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struct irq_desc *desc = irq_to_desc(irq);
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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if (irqd_irq_disabled(data))
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continue;
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/*
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* No handling for now.
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* TBD: Implement a disable function so we can now
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* tell CPU not to respond to these local intr sources.
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* such as ITV,CPEI,MCA etc.
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*/
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if (irqd_is_per_cpu(data))
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continue;
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if (cpumask_any_and(data->affinity, cpu_online_mask)
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>= nr_cpu_ids) {
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/*
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* Save it for phase 2 processing
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*/
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vectors_in_migration[irq] = irq;
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new_cpu = cpumask_any(cpu_online_mask);
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/*
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* Al three are essential, currently WARN_ON.. maybe panic?
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*/
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if (chip && chip->irq_disable &&
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chip->irq_enable && chip->irq_set_affinity) {
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chip->irq_disable(data);
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chip->irq_set_affinity(data,
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cpumask_of(new_cpu), false);
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chip->irq_enable(data);
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} else {
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WARN_ON((!chip || !chip->irq_disable ||
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!chip->irq_enable ||
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!chip->irq_set_affinity));
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}
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}
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}
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}
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void fixup_irqs(void)
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{
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unsigned int irq;
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extern void ia64_process_pending_intr(void);
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extern volatile int time_keeper_id;
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/* Mask ITV to disable timer */
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ia64_set_itv(1 << 16);
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/*
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* Find a new timesync master
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*/
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if (smp_processor_id() == time_keeper_id) {
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time_keeper_id = cpumask_first(cpu_online_mask);
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printk ("CPU %d is now promoted to time-keeper master\n", time_keeper_id);
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}
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/*
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* Phase 1: Locate IRQs bound to this cpu and
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* relocate them for cpu removal.
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*/
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migrate_irqs();
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/*
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* Phase 2: Perform interrupt processing for all entries reported in
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* local APIC.
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*/
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ia64_process_pending_intr();
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/*
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* Phase 3: Now handle any interrupts not captured in local APIC.
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* This is to account for cases that device interrupted during the time the
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* rte was being disabled and re-programmed.
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*/
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for (irq=0; irq < NR_IRQS; irq++) {
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if (vectors_in_migration[irq]) {
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struct pt_regs *old_regs = set_irq_regs(NULL);
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vectors_in_migration[irq]=0;
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generic_handle_irq(irq);
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set_irq_regs(old_regs);
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}
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}
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/*
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* Now let processor die. We do irq disable and max_xtp() to
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* ensure there is no more interrupts routed to this processor.
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* But the local timer interrupt can have 1 pending which we
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* take care in timer_interrupt().
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*/
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max_xtp();
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local_irq_disable();
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}
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#endif
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