ef11bdb3e0
Kabylake is a Intel® Processor containing Intel® HD Graphics
following Skylake.
It is Gen9p5, so it inherits everything from Skylake.
Let's start by adding the platform separated from Skylake
but reusing most of all features, functions etc. Later we
rebase the PCI-ID patch without is_skylake=1
so we don't replace what original Author did there.
Few IS_SKYLAKEs if statements are not being covered by this patch
on purpose:
- Workarounds: Kabylake is derivated from Skylake H0 so no
W/As apply here.
- GuC: A following patch removes Kabylake support with an
explanation: No firmware available yet.
- DMC/CSR: Done in a separated patch since we need to be carefull
and load the version for revision 7 since
Kabylake is Skylake H0.
v2: relative cleaner commit message and added the missed
IS_KABYLAKE to intel_i2c.c as pointed out by Jani.
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
336 lines
11 KiB
C
336 lines
11 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions: *
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "intel_mocs.h"
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#include "intel_lrc.h"
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#include "intel_ringbuffer.h"
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/* structures required */
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struct drm_i915_mocs_entry {
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u32 control_value;
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u16 l3cc_value;
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};
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struct drm_i915_mocs_table {
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u32 size;
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const struct drm_i915_mocs_entry *table;
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};
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/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
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#define LE_CACHEABILITY(value) ((value) << 0)
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#define LE_TGT_CACHE(value) ((value) << 2)
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#define LE_LRUM(value) ((value) << 4)
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#define LE_AOM(value) ((value) << 6)
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#define LE_RSC(value) ((value) << 7)
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#define LE_SCC(value) ((value) << 8)
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#define LE_PFM(value) ((value) << 11)
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#define LE_SCF(value) ((value) << 14)
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/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
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#define L3_ESC(value) ((value) << 0)
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#define L3_SCC(value) ((value) << 1)
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#define L3_CACHEABILITY(value) ((value) << 4)
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/* Helper defines */
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#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
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/* (e)LLC caching options */
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#define LE_PAGETABLE 0
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#define LE_UC 1
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#define LE_WT 2
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#define LE_WB 3
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/* L3 caching options */
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#define L3_DIRECT 0
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#define L3_UC 1
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#define L3_RESERVED 2
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#define L3_WB 3
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/* Target cache */
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#define ELLC 0
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#define LLC 1
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#define LLC_ELLC 2
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/*
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* MOCS tables
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*
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* These are the MOCS tables that are programmed across all the rings.
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* The control value is programmed to all the rings that support the
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* MOCS registers. While the l3cc_values are only programmed to the
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* LNCFCMOCS0 - LNCFCMOCS32 registers.
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*
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* These tables are intended to be kept reasonably consistent across
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* platforms. However some of the fields are not applicable to all of
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* them.
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*
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* Entries not part of the following tables are undefined as far as
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* userspace is concerned and shouldn't be relied upon. For the time
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* being they will be implicitly initialized to the strictest caching
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* configuration (uncached) to guarantee forwards compatibility with
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* userspace programs written against more recent kernels providing
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* additional MOCS entries.
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*
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* NOTE: These tables MUST start with being uncached and the length
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* MUST be less than 63 as the last two registers are reserved
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* by the hardware. These tables are part of the kernel ABI and
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* may only be updated incrementally by adding entries at the
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* end.
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*/
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static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
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/* { 0x00000009, 0x0010 } */
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{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
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/* { 0x00000038, 0x0030 } */
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{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
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/* { 0x0000003b, 0x0030 } */
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{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
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};
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/* NOTE: the LE_TGT_CACHE is not used on Broxton */
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static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
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/* { 0x00000009, 0x0010 } */
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{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
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/* { 0x00000038, 0x0030 } */
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{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
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/* { 0x0000003b, 0x0030 } */
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{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
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LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
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(L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
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};
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/**
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* get_mocs_settings()
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* @dev: DRM device.
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* @table: Output table that will be made to point at appropriate
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* MOCS values for the device.
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*
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* This function will return the values of the MOCS table that needs to
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* be programmed for the platform. It will return the values that need
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* to be programmed and if they need to be programmed.
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*
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* Return: true if there are applicable MOCS settings for the device.
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*/
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static bool get_mocs_settings(struct drm_device *dev,
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struct drm_i915_mocs_table *table)
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{
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bool result = false;
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if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
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table->size = ARRAY_SIZE(skylake_mocs_table);
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table->table = skylake_mocs_table;
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result = true;
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} else if (IS_BROXTON(dev)) {
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table->size = ARRAY_SIZE(broxton_mocs_table);
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table->table = broxton_mocs_table;
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result = true;
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} else {
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WARN_ONCE(INTEL_INFO(dev)->gen >= 9,
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"Platform that should have a MOCS table does not.\n");
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}
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return result;
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}
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/**
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* emit_mocs_control_table() - emit the mocs control table
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* @req: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
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* @reg_base: The base for the engine that needs to be programmed.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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static int emit_mocs_control_table(struct drm_i915_gem_request *req,
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const struct drm_i915_mocs_table *table,
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u32 reg_base)
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{
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struct intel_ringbuffer *ringbuf = req->ringbuf;
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unsigned int index;
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int ret;
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if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
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return -ENODEV;
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ret = intel_logical_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
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if (ret) {
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DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
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return ret;
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}
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intel_logical_ring_emit(ringbuf,
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MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
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for (index = 0; index < table->size; index++) {
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intel_logical_ring_emit(ringbuf, reg_base + index * 4);
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intel_logical_ring_emit(ringbuf,
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table->table[index].control_value);
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}
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/*
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* Ok, now set the unused entries to uncached. These entries
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* are officially undefined and no contract for the contents
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* and settings is given for these entries.
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*
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* Entry 0 in the table is uncached - so we are just writing
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* that value to all the used entries.
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*/
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for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
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intel_logical_ring_emit(ringbuf, reg_base + index * 4);
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intel_logical_ring_emit(ringbuf, table->table[0].control_value);
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}
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intel_logical_ring_emit(ringbuf, MI_NOOP);
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intel_logical_ring_advance(ringbuf);
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return 0;
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}
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/**
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* emit_mocs_l3cc_table() - emit the mocs control table
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* @req: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address. This register set is
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* programmed in pairs.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
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const struct drm_i915_mocs_table *table)
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{
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struct intel_ringbuffer *ringbuf = req->ringbuf;
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unsigned int count;
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unsigned int i;
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u32 value;
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u32 filler = (table->table[0].l3cc_value & 0xffff) |
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((table->table[0].l3cc_value & 0xffff) << 16);
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int ret;
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if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
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return -ENODEV;
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ret = intel_logical_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
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if (ret) {
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DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
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return ret;
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}
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intel_logical_ring_emit(ringbuf,
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MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
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for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
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value = (table->table[count].l3cc_value & 0xffff) |
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((table->table[count + 1].l3cc_value & 0xffff) << 16);
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intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
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intel_logical_ring_emit(ringbuf, value);
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}
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if (table->size & 0x01) {
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/* Odd table size - 1 left over */
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value = (table->table[count].l3cc_value & 0xffff) |
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((table->table[0].l3cc_value & 0xffff) << 16);
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} else
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value = filler;
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/*
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* Now set the rest of the table to uncached - use entry 0 as
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* this will be uncached. Leave the last pair uninitialised as
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* they are reserved by the hardware.
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*/
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for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
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intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
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intel_logical_ring_emit(ringbuf, value);
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value = filler;
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}
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intel_logical_ring_emit(ringbuf, MI_NOOP);
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intel_logical_ring_advance(ringbuf);
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return 0;
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}
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/**
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* intel_rcs_context_init_mocs() - program the MOCS register.
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* @req: Request to set up the MOCS tables for.
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*
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* This function will emit a batch buffer with the values required for
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* programming the MOCS register values for all the currently supported
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* rings.
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*
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* These registers are partially stored in the RCS context, so they are
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* emitted at the same time so that when a context is created these registers
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* are set up. These registers have to be emitted into the start of the
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* context as setting the ELSP will re-init some of these registers back
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* to the hw values.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
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{
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struct drm_i915_mocs_table t;
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int ret;
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if (get_mocs_settings(req->ring->dev, &t)) {
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/* Program the control registers */
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ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);
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if (ret)
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return ret;
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ret = emit_mocs_control_table(req, &t, GEN9_MFX0_MOCS_0);
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if (ret)
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return ret;
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ret = emit_mocs_control_table(req, &t, GEN9_MFX1_MOCS_0);
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if (ret)
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return ret;
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ret = emit_mocs_control_table(req, &t, GEN9_VEBOX_MOCS_0);
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if (ret)
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return ret;
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ret = emit_mocs_control_table(req, &t, GEN9_BLT_MOCS_0);
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if (ret)
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return ret;
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/* Now program the l3cc registers */
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ret = emit_mocs_l3cc_table(req, &t);
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if (ret)
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return ret;
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}
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return 0;
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}
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