271 lines
7.2 KiB
C
271 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <linux/of_address.h>
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#include "sun8i_dw_hdmi.h"
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#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
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#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_POL(val) (val << 8)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
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#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
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#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
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#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
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#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
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#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
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#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47
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/*
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* Address can be actually any value. Here is set to same value as
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* it is set in BSP driver.
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*/
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#define I2C_ADDR 0x69
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static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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struct drm_display_mode *mode)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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u32 val = 0;
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if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
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(mode->flags & DRM_MODE_FLAG_NHSYNC)) {
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val = 0x03;
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}
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK,
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SUN8I_HDMI_PHY_DBG_CTRL_POL(val));
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
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/* power down */
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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dw_hdmi_phy_reset(hdmi);
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dw_hdmi_phy_gen2_pddq(hdmi, 0);
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dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
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/*
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* Values are taken from BSP HDMI driver. Although AW didn't
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* release any documentation, explanation of this values can
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* be found in i.MX 6Dual/6Quad Reference Manual.
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*/
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if (mode->crtc_clock <= 27000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (mode->crtc_clock <= 74250) {
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dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (mode->crtc_clock <= 148500) {
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dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
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} else {
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
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}
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
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dw_hdmi_phy_gen2_txpwron(hdmi, 1);
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return 0;
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};
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static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
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}
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static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
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.init = &sun8i_hdmi_phy_config,
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.disable = &sun8i_hdmi_phy_disable,
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.read_hpd = &dw_hdmi_phy_read_hpd,
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.update_hpd = &dw_hdmi_phy_update_hpd,
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.setup_hpd = &dw_hdmi_phy_setup_hpd,
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};
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void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
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{
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/* enable read access to HDMI controller */
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regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
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SUN8I_HDMI_PHY_READ_EN_MAGIC);
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/* unscramble register offsets */
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regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
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SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
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SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
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/*
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* Set PHY I2C address. It must match to the address set by
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* dw_hdmi_phy_set_slave_addr().
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*/
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
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SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
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}
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const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
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{
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return &sun8i_hdmi_phy_ops;
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}
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static struct regmap_config sun8i_hdmi_phy_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
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.name = "phy"
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};
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static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
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{ .compatible = "allwinner,sun8i-a83t-hdmi-phy" },
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{ /* sentinel */ }
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};
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int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
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{
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struct device *dev = hdmi->dev;
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struct sun8i_hdmi_phy *phy;
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struct resource res;
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void __iomem *regs;
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int ret;
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if (!of_match_node(sun8i_hdmi_phy_of_table, node)) {
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dev_err(dev, "Incompatible HDMI PHY\n");
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return -EINVAL;
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}
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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ret = of_address_to_resource(node, 0, &res);
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if (ret) {
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dev_err(dev, "phy: Couldn't get our resources\n");
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return ret;
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}
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regs = devm_ioremap_resource(dev, &res);
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if (IS_ERR(regs)) {
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dev_err(dev, "Couldn't map the HDMI PHY registers\n");
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return PTR_ERR(regs);
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}
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phy->regs = devm_regmap_init_mmio(dev, regs,
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&sun8i_hdmi_phy_regmap_config);
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if (IS_ERR(phy->regs)) {
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dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
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return PTR_ERR(phy->regs);
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}
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phy->clk_bus = of_clk_get_by_name(node, "bus");
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if (IS_ERR(phy->clk_bus)) {
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dev_err(dev, "Could not get bus clock\n");
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return PTR_ERR(phy->clk_bus);
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}
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phy->clk_mod = of_clk_get_by_name(node, "mod");
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if (IS_ERR(phy->clk_mod)) {
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dev_err(dev, "Could not get mod clock\n");
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ret = PTR_ERR(phy->clk_mod);
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goto err_put_clk_bus;
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}
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phy->rst_phy = of_reset_control_get_shared(node, "phy");
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if (IS_ERR(phy->rst_phy)) {
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dev_err(dev, "Could not get phy reset control\n");
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ret = PTR_ERR(phy->rst_phy);
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goto err_put_clk_mod;
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}
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ret = reset_control_deassert(phy->rst_phy);
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if (ret) {
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dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
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goto err_put_rst_phy;
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}
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ret = clk_prepare_enable(phy->clk_bus);
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if (ret) {
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dev_err(dev, "Cannot enable bus clock: %d\n", ret);
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goto err_deassert_rst_phy;
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}
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ret = clk_prepare_enable(phy->clk_mod);
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if (ret) {
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dev_err(dev, "Cannot enable mod clock: %d\n", ret);
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goto err_disable_clk_bus;
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}
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hdmi->phy = phy;
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return 0;
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err_disable_clk_bus:
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clk_disable_unprepare(phy->clk_bus);
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err_deassert_rst_phy:
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reset_control_assert(phy->rst_phy);
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err_put_rst_phy:
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reset_control_put(phy->rst_phy);
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err_put_clk_mod:
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clk_put(phy->clk_mod);
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err_put_clk_bus:
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clk_put(phy->clk_bus);
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return ret;
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}
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void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
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{
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struct sun8i_hdmi_phy *phy = hdmi->phy;
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clk_disable_unprepare(phy->clk_mod);
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clk_disable_unprepare(phy->clk_bus);
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reset_control_assert(phy->rst_phy);
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reset_control_put(phy->rst_phy);
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clk_put(phy->clk_mod);
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clk_put(phy->clk_bus);
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}
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