![Noam Camus](/assets/img/avatar_default.png)
We need our own implementaions since we lack LLSC support. Our extended ISA provided with optimized solution for all 32bit operations we see in these three headers. Signed-off-by: Noam Camus <noamc@ezchip.com>
222 lines
5.4 KiB
C
222 lines
5.4 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_CMPXCHG_H
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#define __ASM_ARC_CMPXCHG_H
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/smp.h>
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#ifdef CONFIG_ARC_HAS_LLSC
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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unsigned long prev;
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/*
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* Explicit full memory barrier needed before/after as
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* LLOCK/SCOND thmeselves don't provide any such semantics
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*/
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smp_mb();
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__asm__ __volatile__(
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"1: llock %0, [%1] \n"
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" brne %0, %2, 2f \n"
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" scond %3, [%1] \n"
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" bnz 1b \n"
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"2: \n"
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: "=&r"(prev) /* Early clobber, to prevent reg reuse */
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: "r"(ptr), /* Not "m": llock only supports reg direct addr mode */
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"ir"(expected),
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"r"(new) /* can't be "ir". scond can't take LIMM for "b" */
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: "cc", "memory"); /* so that gcc knows memory is being written here */
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smp_mb();
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return prev;
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}
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#elif !defined(CONFIG_ARC_PLAT_EZNPS)
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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unsigned long flags;
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int prev;
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volatile unsigned long *p = ptr;
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/*
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* spin lock/unlock provide the needed smp_mb() before/after
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*/
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atomic_ops_lock(flags);
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prev = *p;
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if (prev == expected)
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*p = new;
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atomic_ops_unlock(flags);
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return prev;
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}
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
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{
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/*
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* Explicit full memory barrier needed before/after
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*/
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smp_mb();
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write_aux_reg(CTOP_AUX_GPA1, expected);
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__asm__ __volatile__(
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" mov r2, %0\n"
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" mov r3, %1\n"
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" .word %2\n"
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" mov %0, r2"
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: "+r"(new)
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: "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3)
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: "r2", "r3", "memory");
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smp_mb();
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return new;
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}
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#endif /* CONFIG_ARC_HAS_LLSC */
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#define cmpxchg(ptr, o, n) ((typeof(*(ptr)))__cmpxchg((ptr), \
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(unsigned long)(o), (unsigned long)(n)))
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/*
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* atomic_cmpxchg is same as cmpxchg
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* LLSC: only different in data-type, semantics are exactly same
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* !LLSC: cmpxchg() has to use an external lock atomic_ops_lock to guarantee
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* semantics, and this lock also happens to be used by atomic_*()
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*/
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#ifndef CONFIG_ARC_PLAT_EZNPS
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/*
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* xchg (reg with memory) based on "Native atomic" EX insn
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*/
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static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
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int size)
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{
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extern unsigned long __xchg_bad_pointer(void);
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switch (size) {
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case 4:
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smp_mb();
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__asm__ __volatile__(
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" ex %0, [%1] \n"
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: "+r"(val)
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: "r"(ptr)
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: "memory");
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smp_mb();
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return val;
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}
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return __xchg_bad_pointer();
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}
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#define _xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
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sizeof(*(ptr))))
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/*
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* xchg() maps directly to ARC EX instruction which guarantees atomicity.
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* However in !LLSC config, it also needs to be use @atomic_ops_lock spinlock
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* due to a subtle reason:
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* - For !LLSC, cmpxchg() needs to use that lock (see above) and there is lot
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* of kernel code which calls xchg()/cmpxchg() on same data (see llist.h)
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* Hence xchg() needs to follow same locking rules.
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*
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* Technically the lock is also needed for UP (boils down to irq save/restore)
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* but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to
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* be disabled thus can't possibly be interrpted/preempted/clobbered by xchg()
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* Other way around, xchg is one instruction anyways, so can't be interrupted
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* as such
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*/
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#if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP)
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#define xchg(ptr, with) \
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({ \
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unsigned long flags; \
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typeof(*(ptr)) old_val; \
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\
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atomic_ops_lock(flags); \
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old_val = _xchg(ptr, with); \
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atomic_ops_unlock(flags); \
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old_val; \
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})
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#else
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#define xchg(ptr, with) _xchg(ptr, with)
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#endif
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#else /* CONFIG_ARC_PLAT_EZNPS */
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static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
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int size)
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{
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extern unsigned long __xchg_bad_pointer(void);
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switch (size) {
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case 4:
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/*
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* Explicit full memory barrier needed before/after
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*/
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smp_mb();
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__asm__ __volatile__(
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" mov r2, %0\n"
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" mov r3, %1\n"
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" .word %2\n"
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" mov %0, r2\n"
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: "+r"(val)
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: "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3)
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: "r2", "r3", "memory");
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smp_mb();
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return val;
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}
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return __xchg_bad_pointer();
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}
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#define xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
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sizeof(*(ptr))))
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#endif /* CONFIG_ARC_PLAT_EZNPS */
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/*
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* "atomic" variant of xchg()
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* REQ: It needs to follow the same serialization rules as other atomic_xxx()
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* Since xchg() doesn't always do that, it would seem that following defintion
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* is incorrect. But here's the rationale:
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* SMP : Even xchg() takes the atomic_ops_lock, so OK.
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* LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC
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* is natively "SMP safe", no serialization required).
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* UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()
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* could clobber them. atomic_xchg() itself would be 1 insn, so it
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* can't be clobbered by others. Thus no serialization required when
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* atomic_xchg is involved.
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*/
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#endif
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