Paulo Zanoni b8fc2f6a18 drm/i915: set the correct eDP aux channel clock divider on DDI ... The cdclk frequency is not always the same, so the value here should be adjusted to match it. Version 2: call intel_ddi_get_cdclk_freq instead of reading CDCLK_FREQ, because the register is just for earlier HW steppings. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2012-10-26 10:24:50 +02:00
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drm	drm/i915: set the correct eDP aux channel clock divider on DDI	2012-10-26 10:24:50 +02:00
stub	i915: select VIDEO_OUTPUT_CONTROL for ACPI_VIDEO	2011-04-13 09:10:25 +10:00
vga	Merge branch 'pci/yinghai-misc' into next	2012-09-24 17:24:11 -06:00
Makefile	gpu: Add Intel GMA500(Poulsbo) Stub Driver	2010-10-26 11:00:13 +10:00