![Mike Turquette](/assets/img/avatar_default.png)
This patch implements a workaround for the DPLL HS divider limitation in OMAP3630 as given by Errata ID: i556. Errata: When PWRDN bit is set, it resets the internal HSDIVIDER divide-by value (Mx). The reset value gets loaded instead of the previous value. The following HSDIVIDERs exhibit above behavior: . DPLL4 : M6 / M5 / M4 / M3 / M2 (CM_CLKEN_PLL[31:26] register bits) . DPLL3 : M3 (CM_CLKEN_PLL[12] register bit). Work Around: It is mandatory to apply the following sequence to ensure the write value will be loaded in DPLL HSDIVIDER FSM: The global sequence when using PWRDN bit is the following: . Disable Mx HSDIVIDER clock output related functional clock enable bits (in CM_FCLKEN_xxx / CM_ICLKEN_xxx) . Enable PWRDN bit of HSDIVIDER . Disable PWRDN bit of HSDIVIDER . Read current HSDIVIDER register value . Write different value in HSDIVIDER register . Write expected value in HSDIVIDER register . Enable Mx HSDIVIDER clock output related functional clocks (CM_FCLKEN_xxx / CM_ICLKEN_xxx) Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Vijaykumar GN <vijaykumar.gn@ti.com> [paul@pwsan.com: updated patch to apply; made workaround function static; marked as being 36xx-specific] Signed-off-by: Paul Walmsley <paul@pwsan.com>
33 lines
1,023 B
C
33 lines
1,023 B
C
/*
|
|
* OMAP3 clock function prototypes and macros
|
|
*
|
|
* Copyright (C) 2007-2009 Texas Instruments, Inc.
|
|
* Copyright (C) 2007-2009 Nokia Corporation
|
|
*/
|
|
|
|
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
|
|
#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
|
|
|
|
int omap3xxx_clk_init(void);
|
|
int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
|
|
int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
|
|
void omap3_clk_lock_dpll5(void);
|
|
|
|
extern struct clk *sdrc_ick_p;
|
|
extern struct clk *arm_fck_p;
|
|
|
|
/* OMAP34xx-specific clkops */
|
|
extern const struct clkops clkops_omap3430es2_ssi_wait;
|
|
extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
|
|
extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
|
|
extern const struct clkops omap3_clkops_noncore_dpll_ops;
|
|
|
|
/* AM35xx-specific clkops */
|
|
extern const struct clkops clkops_am35xx_ipss_module_wait;
|
|
extern const struct clkops clkops_am35xx_ipss_wait;
|
|
|
|
/* OMAP36xx-specific clkops */
|
|
extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
|
|
|
|
#endif
|