47e9dedb72
The KGDB code uses this when switching processors to make sure the icache is in a valid state. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
37 lines
733 B
C
37 lines
733 B
C
/*
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* Blackfin cache control code (simpler control-style functions)
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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/* Invalidate the Entire Data cache by
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* clearing DMC[1:0] bits
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*/
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void blackfin_invalidate_entire_dcache(void)
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{
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u32 dmem = bfin_read_DMEM_CONTROL();
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bfin_write_DMEM_CONTROL(dmem & ~0xc);
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SSYNC();
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bfin_write_DMEM_CONTROL(dmem);
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SSYNC();
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}
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/* Invalidate the Entire Instruction cache by
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* clearing IMC bit
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*/
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void blackfin_invalidate_entire_icache(void)
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{
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u32 imem = bfin_read_IMEM_CONTROL();
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bfin_write_IMEM_CONTROL(imem & ~0x4);
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SSYNC();
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bfin_write_IMEM_CONTROL(imem);
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SSYNC();
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}
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