836 lines
22 KiB
C
836 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <linux/delay.h>
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#include <linux/console.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/genalloc.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/psci.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/suspend.h>
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#include <asm/cacheflush.h>
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#include <asm/fncpy.h>
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#include <asm/mach/map.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/tlb.h>
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#include <uapi/linux/psci.h>
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#include "common.h"
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#include "hardware.h"
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#define MU_SR 0x60
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#define PMPROT 0x8
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#define PMCTRL 0x10
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#define PMSTAT 0x18
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#define SRS 0x20
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#define RPC 0x24
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#define SSRS 0x28
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#define SRIE 0x2c
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#define SRIF 0x30
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#define CSRE 0x34
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#define MR 0x40
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#define PMC1_HSRUN 0x4
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#define PMC1_RUN 0x8
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#define PMC1_VLPR 0xc
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#define PMC1_STOP 0x10
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#define PMC1_VLPS 0x14
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#define PMC1_LLS 0x18
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#define PMC1_VLLS 0x1c
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#define PMC1_STATUS 0x20
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#define PMC1_CTRL 0x24
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#define PMC0_CTRL 0x28
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#define BM_PMPROT_AHSRUN (1 << 7)
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#define BM_PMPROT_AVLP (1 << 5)
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#define BM_PMPROT_ALLS (1 << 3)
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#define BM_PMPROT_AVLLS (1 << 1)
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#define BM_PMCTRL_STOPA (1 << 24)
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#define BM_PMCTRL_PSTOPO (3 << 16)
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#define BM_PMCTRL_RUNM (3 << 8)
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#define BM_PMCTRL_STOPM (7 << 0)
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#define BM_VLPS_RBBEN (1 << 28)
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#define BM_CTRL_LDOEN (1 << 31)
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#define BM_CTRL_LDOOKDIS (1 << 30)
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#define BM_VLLS_MON1P2HVDHP (1 << 5)
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#define BM_VLLS_MON1P2LVDHP (1 << 4)
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#define BP_PMCTRL_STOPM 0
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#define BP_PMCTRL_PSTOPO 16
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#define MX7ULP_MAX_MMDC_IO_NUM 64
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#define MX7ULP_MAX_MMDC_NUM 50
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#define MX7ULP_MAX_IOMUX_NUM 116
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#define MX7ULP_MAX_SELECT_INPUT_NUM 78
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#define IOMUX_START 0x0
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#define SELECT_INPUT_START 0x200
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#define TPM_SC 0x10
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#define TPM_MOD 0x18
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#define TPM_C0SC 0x20
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#define TPM_C0V 0x24
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#define PCC2_ENABLE_PCS_FIRC ((1 << 30) | (3 << 24))
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#define PCC2_ENABLE (1 << 30)
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#define LPUART_BAUD 0x10
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#define LPUART_CTRL 0x18
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#define LPUART_FIFO 0x28
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#define LPUART_WATER 0x2c
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#define GPIO_PDOR 0x0
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#define GPIO_PDDR 0x14
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#define PTC2_LPUART4_TX_OFFSET 0x8
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#define PTC3_LPUART4_RX_OFFSET 0xc
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#define PTC2_LPUART4_TX_INPUT_OFFSET 0x248
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#define PTC3_LPUART4_RX_INPUT_OFFSET 0x24c
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#define LPUART4_MUX_VALUE (4 << 8)
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#define LPUART4_INPUT_VALUE (1)
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#define MU_B_SR_NMIC (1 << 3)
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#define DGO_GPR3 0x60
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#define DGO_GPR4 0x64
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#define ADDR_1M_MASK 0xFFF00000
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static void __iomem *smc1_base;
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static void __iomem *pmc0_base;
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static void __iomem *pmc1_base;
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static void __iomem *tpm5_base;
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static void __iomem *lpuart4_base;
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static void __iomem *iomuxc1_base;
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static void __iomem *pcc2_base;
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static void __iomem *pcc3_base;
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static void __iomem *mu_base;
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static void __iomem *scg1_base;
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static void __iomem *wdog1_base;
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static void __iomem *gpio_base[4];
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static void __iomem *suspend_ocram_base;
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static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base);
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static u32 tpm5_regs[4];
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static u32 lpuart4_regs[4];
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static u32 pcc2_regs[24][2] = {
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{0x20, 0}, {0x3c, 0}, {0x40, 0}, {0x6c, 0},
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{0x84, 0}, {0x90, 0}, {0x94, 0}, {0x98, 0},
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{0x9c, 0}, {0xa4, 0}, {0xa8, 0}, {0xac, 0},
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{0xb0, 0}, {0xb4, 0}, {0xb8, 0}, {0xc4, 0},
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{0xcc, 0}, {0xd0, 0}, {0xd4, 0}, {0xd8, 0},
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{0xdc, 0}, {0xe0, 0}, {0xf4, 0}, {0x10c, 0},
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};
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static u32 pcc3_regs[16][2] = {
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{0x84, 0}, {0x88, 0}, {0x90, 0}, {0x94, 0},
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{0x98, 0}, {0x9c, 0}, {0xa0, 0}, {0xa4, 0},
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{0xa8, 0}, {0xac, 0}, {0xb8, 0}, {0xbc, 0},
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{0xc0, 0}, {0xc4, 0}, {0x140, 0}, {0x144, 0},
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};
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static u32 scg1_offset[17] = {
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0x14, 0x30, 0x40, 0x304,
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0x500, 0x504, 0x508, 0x50c,
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0x510, 0x514, 0x600, 0x604,
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0x608, 0x60c, 0x610, 0x614,
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0x104,
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};
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extern unsigned long iram_tlb_base_addr;
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extern unsigned long iram_tlb_phys_addr;
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/*
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* suspend ocram space layout:
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* ======================== high address ======================
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* .
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* .
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* .
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* ^
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* ^
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* ^
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* imx7ulp_suspend code
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* PM_INFO structure(imx7ulp_cpu_pm_info)
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* ======================== low address =======================
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*/
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struct imx7ulp_pm_socdata {
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u32 ddr_type;
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const char *mmdc_compat;
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const u32 mmdc_io_num;
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const u32 *mmdc_io_offset;
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const u32 mmdc_num;
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const u32 *mmdc_offset;
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};
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static const u32 imx7ulp_mmdc_io_lpddr3_offset[] __initconst = {
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0x0, 0x4, 0x8, 0xc,
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0x10, 0x14, 0x18, 0x1c,
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0x20, 0x24, 0x28, 0x2c,
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0x30, 0x34, 0x38, 0x3c,
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0x40, 0x44, 0x48, 0x4c,
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0x50, 0x54, 0x58, 0x5c,
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0x60, 0x64, 0x68, 0x6c,
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0x70, 0x74, 0x78, 0x7c,
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0x80, 0x84, 0x88, 0x8c,
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0x90, 0x94, 0x98, 0x9c,
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0xa0, 0xa4, 0xa8, 0xac,
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0xb0, 0xb4, 0xb8, 0xbc,
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0xc0, 0xc4, 0xc8, 0xcc,
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0xd0, 0xd4, 0xd8, 0xdc,
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0xe8, 0xf8, 0xfc, 0x120,
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0x124,
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};
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static const u32 imx7ulp_mmdc_lpddr3_offset[] __initconst = {
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0x01c, 0x800, 0x85c, 0x890,
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0x848, 0x850, 0x81c, 0x820,
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0x824, 0x828, 0x82c, 0x830,
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0x834, 0x838, 0x8c0, 0x8b8,
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0x004, 0x00c, 0x010, 0x038,
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0x014, 0x018, 0x02c, 0x030,
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0x040, 0x000, 0x01c, 0x01c,
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0x01c, 0x01c, 0x01c, 0x01c,
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0x01c, 0x01c, 0x01c, 0x01c,
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0x01c, 0x01c, 0x83c, 0x020,
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0x800, 0x004, 0x404, 0x01c,
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};
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static const u32 imx7ulp_lpddr3_script[] __initconst = {
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0x00008000, 0xA1390003, 0x0D3900A0, 0x00400000,
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0x40404040, 0x40404040, 0x33333333, 0x33333333,
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0x33333333, 0x33333333, 0xf3333333, 0xf3333333,
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0xf3333333, 0xf3333333, 0x24922492, 0x00000800,
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0x00020052, 0x292C42F3, 0x00100A22, 0x00120556,
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0x00C700DB, 0x00211718, 0x0F9F26D2, 0x009F0E10,
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0x0000003F, 0xC3190000, 0x00008050, 0x00008058,
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0x003F8030, 0x003F8038, 0xFF0A8030, 0xFF0A8038,
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0x04028030, 0x04028038, 0x83018030, 0x83018038,
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0x01038030, 0x01038038, 0x20000000, 0x00001800,
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0xA1310000, 0x00020052, 0x00011006, 0x00000000,
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};
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static const struct imx7ulp_pm_socdata imx7ulp_lpddr3_pm_data __initconst = {
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.mmdc_compat = "fsl,imx7ulp-mmdc",
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.mmdc_io_num = ARRAY_SIZE(imx7ulp_mmdc_io_lpddr3_offset),
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.mmdc_io_offset = imx7ulp_mmdc_io_lpddr3_offset,
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.mmdc_num = ARRAY_SIZE(imx7ulp_mmdc_lpddr3_offset),
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.mmdc_offset = imx7ulp_mmdc_lpddr3_offset,
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};
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/*
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* This structure is for passing necessary data for low level ocram
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* suspend code(arch/arm/mach-imx/suspend-imx7ulp.S), if this struct
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* definition is changed, the offset definition in
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* arch/arm/mach-imx/suspend-imx7ulp.S must be also changed accordingly,
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* otherwise, the suspend to sram function will be broken!
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*/
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struct imx7ulp_cpu_pm_info {
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u32 m4_reserve0;
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u32 m4_reserve1;
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u32 m4_reserve2;
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phys_addr_t pbase; /* The physical address of pm_info. */
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phys_addr_t resume_addr; /* The physical resume address for asm code */
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u32 pm_info_size; /* Size of pm_info. */
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void __iomem *sim_base;
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void __iomem *scg1_base;
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void __iomem *mmdc_base;
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void __iomem *mmdc_io_base;
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void __iomem *smc1_base;
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u32 scg1[17];
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u32 ttbr1; /* Store TTBR1 */
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u32 gpio[4][2];
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u32 iomux_num; /* Number of IOs which need saved/restored. */
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u32 iomux_val[MX7ULP_MAX_IOMUX_NUM]; /* To save value */
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u32 select_input_num; /* Number of select input which need saved/restored. */
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u32 select_input_val[MX7ULP_MAX_SELECT_INPUT_NUM]; /* To save value */
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u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
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u32 mmdc_io_val[MX7ULP_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
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u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */
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u32 mmdc_val[MX7ULP_MAX_MMDC_NUM][2];
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} __aligned(8);
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static struct imx7ulp_cpu_pm_info *pm_info;
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static void __iomem *aips1_base;
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static void __iomem *aips2_base;
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static void __iomem *aips3_base;
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static void __iomem *aips4_base;
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static void __iomem *aips5_base;
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static const char * const low_power_ocram_match[] __initconst = {
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"fsl,lpm-sram",
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NULL
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};
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static void imx7ulp_gpio_save(void)
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{
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int i;
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for (i = 0; i < 4; i++) {
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pm_info->gpio[i][0] = readl_relaxed(gpio_base[i] + GPIO_PDOR);
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pm_info->gpio[i][1] = readl_relaxed(gpio_base[i] + GPIO_PDDR);
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}
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}
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static void imx7ulp_scg1_save(void)
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{
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int i;
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for (i = 0; i < 17; i++)
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pm_info->scg1[i] = readl_relaxed(scg1_base + scg1_offset[i]);
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}
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static void imx7ulp_pcc3_save(void)
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{
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int i;
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for (i = 0; i < 16; i++)
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pcc3_regs[i][1] = readl_relaxed(pcc3_base + pcc3_regs[i][0]);
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}
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static void imx7ulp_pcc3_restore(void)
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{
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int i;
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for (i = 0; i < 16; i++)
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writel_relaxed(pcc3_regs[i][1], pcc3_base + pcc3_regs[i][0]);
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}
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static void imx7ulp_pcc2_save(void)
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{
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int i;
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for (i = 0; i < 24; i++)
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pcc2_regs[i][1] = readl_relaxed(pcc2_base + pcc2_regs[i][0]);
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}
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static void imx7ulp_pcc2_restore(void)
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{
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int i;
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for (i = 0; i < 24; i++)
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writel_relaxed(pcc2_regs[i][1], pcc2_base + pcc2_regs[i][0]);
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}
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static inline void imx7ulp_iomuxc_save(void)
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{
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int i;
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pm_info->iomux_num = MX7ULP_MAX_IOMUX_NUM;
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pm_info->select_input_num = MX7ULP_MAX_SELECT_INPUT_NUM;
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for (i = 0; i < pm_info->iomux_num; i++)
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pm_info->iomux_val[i] =
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readl_relaxed(iomuxc1_base +
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IOMUX_START + i * 0x4);
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for (i = 0; i < pm_info->select_input_num; i++)
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pm_info->select_input_val[i] =
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readl_relaxed(iomuxc1_base +
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SELECT_INPUT_START + i * 0x4);
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}
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static void imx7ulp_lpuart_save(void)
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{
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lpuart4_regs[0] = readl_relaxed(lpuart4_base + LPUART_BAUD);
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lpuart4_regs[1] = readl_relaxed(lpuart4_base + LPUART_FIFO);
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lpuart4_regs[2] = readl_relaxed(lpuart4_base + LPUART_WATER);
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lpuart4_regs[3] = readl_relaxed(lpuart4_base + LPUART_CTRL);
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}
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static void imx7ulp_lpuart_restore(void)
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{
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writel_relaxed(LPUART4_MUX_VALUE,
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iomuxc1_base + PTC2_LPUART4_TX_OFFSET);
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writel_relaxed(LPUART4_MUX_VALUE,
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iomuxc1_base + PTC3_LPUART4_RX_OFFSET);
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writel_relaxed(LPUART4_INPUT_VALUE,
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iomuxc1_base + PTC2_LPUART4_TX_INPUT_OFFSET);
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writel_relaxed(LPUART4_INPUT_VALUE,
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iomuxc1_base + PTC3_LPUART4_RX_INPUT_OFFSET);
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writel_relaxed(lpuart4_regs[0], lpuart4_base + LPUART_BAUD);
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writel_relaxed(lpuart4_regs[1], lpuart4_base + LPUART_FIFO);
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writel_relaxed(lpuart4_regs[2], lpuart4_base + LPUART_WATER);
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writel_relaxed(lpuart4_regs[3], lpuart4_base + LPUART_CTRL);
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}
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static void imx7ulp_tpm_save(void)
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{
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tpm5_regs[0] = readl_relaxed(tpm5_base + TPM_SC);
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tpm5_regs[1] = readl_relaxed(tpm5_base + TPM_MOD);
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tpm5_regs[2] = readl_relaxed(tpm5_base + TPM_C0SC);
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tpm5_regs[3] = readl_relaxed(tpm5_base + TPM_C0V);
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}
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static void imx7ulp_tpm_restore(void)
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{
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writel_relaxed(tpm5_regs[0], tpm5_base + TPM_SC);
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writel_relaxed(tpm5_regs[1], tpm5_base + TPM_MOD);
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writel_relaxed(tpm5_regs[2], tpm5_base + TPM_C0SC);
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writel_relaxed(tpm5_regs[3], tpm5_base + TPM_C0V);
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}
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static void imx7ulp_set_dgo(u32 val)
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{
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writel_relaxed(val, pm_info->sim_base + DGO_GPR3);
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writel_relaxed(val, pm_info->sim_base + DGO_GPR4);
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}
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int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
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{
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u32 val1 = BM_PMPROT_AHSRUN | BM_PMPROT_AVLP | BM_PMPROT_AVLLS;
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u32 val2 = readl_relaxed(smc1_base + PMCTRL);
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u32 val3 = readl_relaxed(pmc0_base + PMC0_CTRL);
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val2 &= ~(BM_PMCTRL_RUNM |
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BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO);
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val3 |= BM_CTRL_LDOOKDIS;
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switch (mode) {
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case ULP_PM_RUN:
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/* system/bus clock enabled */
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val2 |= 0x3 << BP_PMCTRL_PSTOPO;
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break;
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case ULP_PM_WAIT:
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/* system clock disabled, bus clock enabled */
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val2 |= 0x2 << BP_PMCTRL_PSTOPO;
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break;
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case ULP_PM_STOP:
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/* system/bus clock disabled */
|
|
val2 |= 0x1 << BP_PMCTRL_PSTOPO;
|
|
break;
|
|
case ULP_PM_VLPS:
|
|
val2 |= 0x2 << BP_PMCTRL_STOPM;
|
|
break;
|
|
case ULP_PM_VLLS:
|
|
val2 |= 0x4 << BP_PMCTRL_STOPM;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
writel_relaxed(val1, smc1_base + PMPROT);
|
|
writel_relaxed(val2, smc1_base + PMCTRL);
|
|
writel_relaxed(val3, pmc0_base + PMC0_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define MX7ULP_SUSPEND_POWERDWN_PARAM \
|
|
((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
|
|
(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
|
|
(PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT))
|
|
|
|
#define MX7ULP_SUSPEND_STANDBY_PARAM \
|
|
((0 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
|
|
(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
|
|
(PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT))
|
|
|
|
static int imx7ulp_suspend_finish(unsigned long val)
|
|
{
|
|
u32 state;
|
|
|
|
if (val == 0)
|
|
state = MX7ULP_SUSPEND_POWERDWN_PARAM;
|
|
else
|
|
state = MX7ULP_SUSPEND_STANDBY_PARAM;
|
|
|
|
if (psci_ops.cpu_suspend)
|
|
return psci_ops.cpu_suspend(state, __pa(cpu_resume));
|
|
|
|
imx7ulp_suspend_in_ocram_fn(suspend_ocram_base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void imx7ulp_wdog_refresh(void)
|
|
{
|
|
/*
|
|
* On revision 2.2, wdog2 is by default disabled when out of
|
|
* reset, so here, we ONLY refresh wdog1.
|
|
*/
|
|
writel_relaxed(0xA602, wdog1_base + 0x4);
|
|
writel_relaxed(0xB480, wdog1_base + 0x4);
|
|
}
|
|
|
|
static int imx7ulp_pm_enter(suspend_state_t state)
|
|
{
|
|
switch (state) {
|
|
case PM_SUSPEND_STANDBY:
|
|
if (psci_ops.cpu_suspend)
|
|
/* Zzz ... */
|
|
cpu_suspend(1, imx7ulp_suspend_finish);
|
|
else {
|
|
imx7ulp_set_lpm(ULP_PM_VLPS);
|
|
writel_relaxed(
|
|
readl_relaxed(pmc1_base + PMC1_VLPS) | BM_VLPS_RBBEN,
|
|
pmc1_base + PMC1_VLPS);
|
|
|
|
/* Zzz ... */
|
|
cpu_suspend(0, imx7ulp_suspend_finish);
|
|
|
|
writel_relaxed(
|
|
readl_relaxed(pmc1_base + PMC1_VLPS) & ~BM_VLPS_RBBEN,
|
|
pmc1_base + PMC1_VLPS);
|
|
imx7ulp_set_lpm(ULP_PM_RUN);
|
|
}
|
|
break;
|
|
case PM_SUSPEND_MEM:
|
|
if (psci_ops.cpu_suspend) {
|
|
/* Zzz ... */
|
|
cpu_suspend(0, imx7ulp_suspend_finish);
|
|
} else {
|
|
imx7ulp_gpio_save();
|
|
imx7ulp_scg1_save();
|
|
imx7ulp_pcc2_save();
|
|
imx7ulp_pcc3_save();
|
|
imx7ulp_tpm_save();
|
|
if (!console_suspend_enabled)
|
|
imx7ulp_lpuart_save();
|
|
imx7ulp_iomuxc_save();
|
|
imx7ulp_set_lpm(ULP_PM_VLLS);
|
|
|
|
/* Zzz ... */
|
|
cpu_suspend(0, imx7ulp_suspend_finish);
|
|
|
|
imx7ulp_pcc2_restore();
|
|
imx7ulp_pcc3_restore();
|
|
if (!console_suspend_enabled)
|
|
imx7ulp_lpuart_restore();
|
|
imx7ulp_set_dgo(0);
|
|
imx7ulp_tpm_restore();
|
|
imx7ulp_set_lpm(ULP_PM_RUN);
|
|
}
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
imx7ulp_wdog_refresh();
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Put CA7 into VLLS mode before M4 power off CA7 */
|
|
void imx7ulp_poweroff(void)
|
|
{
|
|
imx7ulp_set_lpm(ULP_PM_VLLS);
|
|
cpu_suspend(0, imx7ulp_suspend_finish);
|
|
}
|
|
|
|
static int imx7ulp_pm_valid(suspend_state_t state)
|
|
{
|
|
return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
|
|
}
|
|
|
|
static const struct platform_suspend_ops imx7ulp_pm_ops = {
|
|
.enter = imx7ulp_pm_enter,
|
|
.valid = imx7ulp_pm_valid,
|
|
};
|
|
|
|
static int __init imx7ulp_suspend_init(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
suspend_set_ops(&imx7ulp_pm_ops);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct map_desc iram_tlb_io_desc __initdata = {
|
|
/* .virtual and .pfn are run-time assigned */
|
|
.length = SZ_1M,
|
|
.type = MT_MEMORY_RWX_NONCACHED,
|
|
};
|
|
|
|
static int __init imx7ulp_dt_find_lpsram(unsigned long node, const char *uname,
|
|
int depth, void *data)
|
|
{
|
|
unsigned long lpram_addr;
|
|
const __be32 *prop = of_get_flat_dt_prop(node, "reg", NULL);
|
|
|
|
if (of_flat_dt_match(node, low_power_ocram_match)) {
|
|
if (!prop)
|
|
return -EINVAL;
|
|
|
|
lpram_addr = be32_to_cpup(prop);
|
|
|
|
/* We need to create a 1M page table entry. */
|
|
iram_tlb_io_desc.virtual =
|
|
IMX_IO_P2V(lpram_addr & ADDR_1M_MASK);
|
|
iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & ADDR_1M_MASK);
|
|
iram_tlb_phys_addr = lpram_addr;
|
|
iram_tlb_base_addr = IMX_IO_P2V(lpram_addr);
|
|
iotable_init(&iram_tlb_io_desc, 1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init imx7ulp_pm_map_io(void)
|
|
{
|
|
/*
|
|
* Get the address of IRAM or OCRAM to be used by the low
|
|
* power code from the device tree.
|
|
*/
|
|
WARN_ON(of_scan_flat_dt(imx7ulp_dt_find_lpsram, NULL));
|
|
|
|
/* Return if no IRAM space is allocated for suspend/resume code. */
|
|
if (!iram_tlb_base_addr) {
|
|
pr_warn("No valid ocram available for suspend/resume!\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata
|
|
*socdata)
|
|
{
|
|
struct device_node *np;
|
|
unsigned long sram_paddr = 0;
|
|
const u32 *mmdc_offset_array;
|
|
const u32 *mmdc_io_offset_array;
|
|
unsigned long i, j;
|
|
int ret;
|
|
|
|
if (psci_ops.cpu_suspend) {
|
|
aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M);
|
|
aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M);
|
|
aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M);
|
|
aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M);
|
|
aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M);
|
|
} else {
|
|
/* Set all entries to 0 except first 3 words reserved for M4. */
|
|
memset((void *)iram_tlb_base_addr, 0, MX7ULP_IRAM_TLB_SIZE);
|
|
|
|
/*
|
|
* Make sure the IRAM virtual address has a mapping in the IRAM
|
|
* page table.
|
|
*
|
|
* Only use the top 12 bits [31-20] when storing the physical
|
|
* address in the page table as only these bits are required
|
|
* for 1M mapping.
|
|
*/
|
|
j = ((iram_tlb_base_addr >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
(iram_tlb_phys_addr & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
/*
|
|
* Make sure the AIPS1 virtual address has a mapping in the
|
|
* IRAM page table.
|
|
*/
|
|
aips1_base = ioremap(MX7ULP_AIPS1_BASE_ADDR, SZ_1M);
|
|
j = (((u32)aips1_base >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
((MX7ULP_AIPS1_BASE_ADDR) & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
/*
|
|
* Make sure the AIPS2 virtual address has a mapping in the
|
|
* IRAM page table.
|
|
*/
|
|
aips2_base = ioremap(MX7ULP_AIPS2_BASE_ADDR, SZ_1M);
|
|
j = (((u32)aips2_base >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
((MX7ULP_AIPS2_BASE_ADDR) & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
/*
|
|
* Make sure the AIPS3 virtual address has a mapping in the
|
|
* IRAM page table.
|
|
*/
|
|
aips3_base = ioremap(MX7ULP_AIPS3_BASE_ADDR, SZ_1M);
|
|
j = (((u32)aips3_base >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
((MX7ULP_AIPS3_BASE_ADDR) & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
/*
|
|
* Make sure the AIPS4 virtual address has a mapping in the
|
|
* IRAM page table.
|
|
*/
|
|
aips4_base = ioremap(MX7ULP_AIPS4_BASE_ADDR, SZ_1M);
|
|
j = (((u32)aips4_base >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
((MX7ULP_AIPS4_BASE_ADDR) & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
/*
|
|
* Make sure the AIPS5 virtual address has a mapping in the
|
|
* IRAM page table.
|
|
*/
|
|
aips5_base = ioremap(MX7ULP_AIPS5_BASE_ADDR, SZ_1M);
|
|
j = (((u32)aips5_base >> 20) << 2) / 4;
|
|
*((unsigned long *)iram_tlb_base_addr + j) =
|
|
((MX7ULP_AIPS5_BASE_ADDR) & ADDR_1M_MASK) |
|
|
TT_ATTRIB_NON_CACHEABLE_1M;
|
|
}
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
|
|
smc1_base = of_iomap(np, 0);
|
|
WARN_ON(!smc1_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0");
|
|
pmc0_base = of_iomap(np, 0);
|
|
WARN_ON(!pmc0_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc1");
|
|
pmc1_base = of_iomap(np, 0);
|
|
WARN_ON(!pmc1_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-tpm");
|
|
tpm5_base = of_iomap(np, 0);
|
|
WARN_ON(!tpm5_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-lpuart");
|
|
lpuart4_base = of_iomap(np, 0);
|
|
WARN_ON(!lpuart4_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc2");
|
|
pcc2_base = of_iomap(np, 0);
|
|
WARN_ON(!pcc2_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pcc3");
|
|
pcc3_base = of_iomap(np, 0);
|
|
WARN_ON(!pcc3_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-iomuxc1");
|
|
iomuxc1_base = of_iomap(np, 0);
|
|
WARN_ON(!iomuxc1_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-scg1");
|
|
scg1_base = of_iomap(np, 0);
|
|
WARN_ON(!scg1_base);
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-wdt");
|
|
wdog1_base = of_iomap(np, 0);
|
|
WARN_ON(!wdog1_base);
|
|
|
|
np = NULL;
|
|
for (i = 0; i < 4; i++) {
|
|
np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio");
|
|
gpio_base[i] = of_iomap(np, 1);
|
|
WARN_ON(!gpio_base[i]);
|
|
}
|
|
|
|
if (psci_ops.cpu_suspend) {
|
|
pm_info = kzalloc(SZ_16K, GFP_KERNEL);
|
|
if (!pm_info)
|
|
panic("pm info allocation failed\n");
|
|
} else {
|
|
/*
|
|
* 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB,
|
|
* The lower 8K is not used, so use the lower 8K for IRAM code and
|
|
* pm_info.
|
|
*
|
|
*/
|
|
sram_paddr = iram_tlb_phys_addr;
|
|
|
|
/* Make sure sram_paddr is 8 byte aligned. */
|
|
if ((uintptr_t)(sram_paddr) & (FNCPY_ALIGN - 1))
|
|
sram_paddr += FNCPY_ALIGN - sram_paddr % (FNCPY_ALIGN);
|
|
|
|
/* Get the virtual address of the suspend code. */
|
|
suspend_ocram_base = (void *)IMX_IO_P2V(sram_paddr);
|
|
|
|
pm_info = suspend_ocram_base;
|
|
}
|
|
pm_info->pbase = sram_paddr;
|
|
pm_info->resume_addr = virt_to_phys(imx7ulp_cpu_resume);
|
|
pm_info->pm_info_size = sizeof(*pm_info);
|
|
|
|
pm_info->scg1_base = aips2_base +
|
|
(MX7ULP_SCG1_BASE_ADDR & ~ADDR_1M_MASK);
|
|
pm_info->smc1_base = aips3_base +
|
|
(MX7ULP_SMC1_BASE_ADDR & ~ADDR_1M_MASK);
|
|
pm_info->mmdc_base = aips4_base +
|
|
(MX7ULP_MMDC_BASE_ADDR & ~ADDR_1M_MASK);
|
|
pm_info->mmdc_io_base = aips4_base +
|
|
(MX7ULP_MMDC_IO_BASE_ADDR & ~ADDR_1M_MASK);
|
|
pm_info->sim_base = aips5_base +
|
|
(MX7ULP_SIM_BASE_ADDR & ~ADDR_1M_MASK);
|
|
|
|
pm_info->mmdc_io_num = socdata->mmdc_io_num;
|
|
mmdc_io_offset_array = socdata->mmdc_io_offset;
|
|
pm_info->mmdc_num = socdata->mmdc_num;
|
|
mmdc_offset_array = socdata->mmdc_offset;
|
|
|
|
for (i = 0; i < pm_info->mmdc_io_num; i++) {
|
|
pm_info->mmdc_io_val[i][0] =
|
|
mmdc_io_offset_array[i];
|
|
pm_info->mmdc_io_val[i][1] =
|
|
readl_relaxed(pm_info->mmdc_io_base +
|
|
mmdc_io_offset_array[i]);
|
|
}
|
|
|
|
/* initialize MMDC settings */
|
|
for (i = 0; i < pm_info->mmdc_num; i++)
|
|
pm_info->mmdc_val[i][0] =
|
|
mmdc_offset_array[i];
|
|
|
|
for (i = 0; i < pm_info->mmdc_num; i++)
|
|
pm_info->mmdc_val[i][1] = imx7ulp_lpddr3_script[i];
|
|
|
|
if (!psci_ops.cpu_suspend) {
|
|
imx7ulp_suspend_in_ocram_fn = fncpy(
|
|
suspend_ocram_base + sizeof(*pm_info),
|
|
&imx7ulp_suspend,
|
|
MX7ULP_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_SUSPEND)) {
|
|
ret = imx7ulp_suspend_init();
|
|
if (ret)
|
|
pr_warn("%s: No DDR LPM support with suspend %d!\n",
|
|
__func__, ret);
|
|
}
|
|
}
|
|
|
|
void __init imx7ulp_pm_init(void)
|
|
{
|
|
imx7ulp_pm_common_init(&imx7ulp_lpddr3_pm_data);
|
|
imx7ulp_set_lpm(ULP_PM_RUN);
|
|
}
|
|
|
|
static irqreturn_t imx7ulp_nmi_isr(int irq, void *param)
|
|
{
|
|
writel_relaxed(readl_relaxed(mu_base + MU_SR) | MU_B_SR_NMIC,
|
|
mu_base + MU_SR);
|
|
pm_system_wakeup();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void imx7ulp_enable_nmi(void)
|
|
{
|
|
struct device_node *np;
|
|
int irq, ret;
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-nmi");
|
|
mu_base = of_iomap(np, 0);
|
|
WARN_ON(!mu_base);
|
|
irq = of_irq_get(np, 0);
|
|
ret = request_irq(irq, imx7ulp_nmi_isr,
|
|
IRQF_NO_SUSPEND, "imx7ulp-nmi", NULL);
|
|
if (ret) {
|
|
pr_err("%s: register interrupt %d failed, rc %d\n",
|
|
__func__, irq, ret);
|
|
return;
|
|
}
|
|
}
|