318 lines
7.4 KiB
C
318 lines
7.4 KiB
C
/*
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* Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file ipu_pixel_clk.c
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*
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* @brief IPU pixel clock implementation
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*
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* @ingroup IPU
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/ipu-v3.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "ipu_prv.h"
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#include "ipu_regs.h"
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/*
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* muxd clock implementation
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*/
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struct clk_di_mux {
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struct clk_hw hw;
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u8 ipu_id;
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u8 di_id;
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u8 flags;
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u8 index;
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};
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#define to_clk_di_mux(_hw) container_of(_hw, struct clk_di_mux, hw)
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static int _ipu_pixel_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_di_mux *mux = to_clk_di_mux(hw);
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struct ipu_soc *ipu = ipu_get_soc(mux->ipu_id);
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u32 di_gen;
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di_gen = ipu_di_read(ipu, mux->di_id, DI_GENERAL);
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if (index == 0)
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/* ipu1_clk or ipu2_clk internal clk */
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di_gen &= ~DI_GEN_DI_CLK_EXT;
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else
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di_gen |= DI_GEN_DI_CLK_EXT;
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ipu_di_write(ipu, mux->di_id, di_gen, DI_GENERAL);
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mux->index = index;
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pr_debug("ipu_pixel_clk: di_clk_ext:0x%x, di_gen reg:0x%x.\n",
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!(di_gen & DI_GEN_DI_CLK_EXT), di_gen);
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return 0;
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}
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static u8 _ipu_pixel_clk_get_parent(struct clk_hw *hw)
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{
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struct clk_di_mux *mux = to_clk_di_mux(hw);
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return mux->index;
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}
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const struct clk_ops clk_mux_di_ops = {
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.get_parent = _ipu_pixel_clk_get_parent,
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.set_parent = _ipu_pixel_clk_set_parent,
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};
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struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents, unsigned long flags,
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u8 ipu_id, u8 di_id, u8 clk_mux_flags)
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{
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struct clk_di_mux *mux;
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struct clk *clk;
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struct clk_init_data init;
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mux = kzalloc(sizeof(struct clk_di_mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_mux_di_ops;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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mux->ipu_id = ipu_id;
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mux->di_id = di_id;
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mux->flags = clk_mux_flags | CLK_SET_RATE_PARENT;
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mux->hw.init = &init;
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clk = clk_register(dev, &mux->hw);
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if (IS_ERR(clk))
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kfree(mux);
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return clk;
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}
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/*
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* Gated clock implementation
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*/
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struct clk_di_div {
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struct clk_hw hw;
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u8 ipu_id;
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u8 di_id;
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u8 flags;
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};
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#define to_clk_di_div(_hw) container_of(_hw, struct clk_di_div, hw)
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static unsigned long _ipu_pixel_clk_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_di_div *di_div = to_clk_di_div(hw);
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struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
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u32 div;
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u64 final_rate = (unsigned long long)parent_rate * 16;
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_ipu_get(ipu);
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div = ipu_di_read(ipu, di_div->di_id, DI_BS_CLKGEN0);
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_ipu_put(ipu);
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pr_debug("ipu_di%d read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
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di_div->di_id, div, final_rate, parent_rate);
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if (div == 0)
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return 0;
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do_div(final_rate, div);
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return (unsigned long)final_rate;
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}
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static long _ipu_pixel_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_clk_rate)
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{
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u64 div, final_rate;
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u32 remainder;
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u64 parent_rate = (unsigned long long)(*parent_clk_rate) * 16;
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/*
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* Calculate divider
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* Fractional part is 4 bits,
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* so simply multiply by 2^4 to get fractional part.
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*/
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div = parent_rate;
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remainder = do_div(div, rate);
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/* Round the divider value */
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if (remainder > (rate/2))
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div++;
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if (div < 0x10) /* Min DI disp clock divider is 1 */
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div = 0x10;
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if (div & ~0xFEF)
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div &= 0xFF8;
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else {
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/* Round up divider if it gets us closer to desired pix clk */
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if ((div & 0xC) == 0xC) {
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div += 0x10;
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div &= ~0xF;
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}
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}
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final_rate = parent_rate;
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do_div(final_rate, div);
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return final_rate;
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}
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static int _ipu_pixel_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_clk_rate)
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{
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struct clk_di_div *di_div = to_clk_di_div(hw);
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struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
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u64 div, parent_rate;
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u32 remainder;
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parent_rate = (unsigned long long)parent_clk_rate * 16;
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div = parent_rate;
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remainder = do_div(div, rate);
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/* Round the divider value */
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if (remainder > (rate/2))
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div++;
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/* Round up divider if it gets us closer to desired pix clk */
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if ((div & 0xC) == 0xC) {
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div += 0x10;
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div &= ~0xF;
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}
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if (div > 0x1000)
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pr_err("Overflow, di:%d, DI_BS_CLKGEN0 div:0x%x\n",
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di_div->di_id, (u32)div);
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_ipu_get(ipu);
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ipu_di_write(ipu, di_div->di_id, (u32)div, DI_BS_CLKGEN0);
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/* Setup pixel clock timing */
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/* FIXME: needs to be more flexible */
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/* Down time is half of period */
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ipu_di_write(ipu, di_div->di_id, ((u32)div / 16) << 16, DI_BS_CLKGEN1);
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_ipu_put(ipu);
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return 0;
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}
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static struct clk_ops clk_div_ops = {
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.recalc_rate = _ipu_pixel_clk_div_recalc_rate,
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.round_rate = _ipu_pixel_clk_div_round_rate,
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.set_rate = _ipu_pixel_clk_div_set_rate,
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};
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struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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u8 ipu_id, u8 di_id, u8 clk_div_flags)
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{
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struct clk_di_div *di_div;
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struct clk *clk;
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struct clk_init_data init;
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di_div = kzalloc(sizeof(struct clk_di_div), GFP_KERNEL);
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if (!di_div)
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return ERR_PTR(-ENOMEM);
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/* struct clk_di_div assignments */
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di_div->ipu_id = ipu_id;
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di_div->di_id = di_id;
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di_div->flags = clk_div_flags;
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init.name = name;
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init.ops = &clk_div_ops;
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init.flags = flags | CLK_SET_RATE_PARENT;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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di_div->hw.init = &init;
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clk = clk_register(dev, &di_div->hw);
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if (IS_ERR(clk))
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kfree(di_div);
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return clk;
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}
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/*
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* Gated clock implementation
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*/
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struct clk_di_gate {
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struct clk_hw hw;
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u8 ipu_id;
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u8 di_id;
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u8 flags;
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};
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#define to_clk_di_gate(_hw) container_of(_hw, struct clk_di_gate, hw)
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static int _ipu_pixel_clk_enable(struct clk_hw *hw)
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{
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struct clk_di_gate *gate = to_clk_di_gate(hw);
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struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
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u32 disp_gen;
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disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
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disp_gen |= gate->di_id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
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ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
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return 0;
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}
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static void _ipu_pixel_clk_disable(struct clk_hw *hw)
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{
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struct clk_di_gate *gate = to_clk_di_gate(hw);
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struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
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u32 disp_gen;
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disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
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disp_gen &= gate->di_id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
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ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
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}
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static struct clk_ops clk_gate_di_ops = {
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.enable = _ipu_pixel_clk_enable,
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.disable = _ipu_pixel_clk_disable,
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};
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struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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u8 ipu_id, u8 di_id, u8 clk_gate_flags)
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{
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struct clk_di_gate *gate;
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struct clk *clk;
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struct clk_init_data init;
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gate = kzalloc(sizeof(struct clk_di_gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->ipu_id = ipu_id;
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gate->di_id = di_id;
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gate->flags = clk_gate_flags;
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init.name = name;
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init.ops = &clk_gate_di_ops;
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init.flags = flags | CLK_SET_RATE_PARENT;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->hw.init = &init;
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clk = clk_register(dev, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}
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