481 lines
22 KiB
C
481 lines
22 KiB
C
/*
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* Freescale PRE Register Definitions
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*
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* Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ARCH_ARM___PRE_H
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#define __ARCH_ARM___PRE_H
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#define HW_PRE_CTRL (0x00000000)
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#define HW_PRE_CTRL_SET (0x00000004)
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#define HW_PRE_CTRL_CLR (0x00000008)
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#define HW_PRE_CTRL_TOG (0x0000000c)
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#define BM_PRE_CTRL_SFTRST 0x80000000
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#define BF_PRE_CTRL_SFTRST(v) \
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(((v) << 31) & BM_PRE_CTRL_SFTRST)
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#define BM_PRE_CTRL_CLKGATE 0x40000000
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#define BF_PRE_CTRL_CLKGATE(v) \
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(((v) << 30) & BM_PRE_CTRL_CLKGATE)
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#define BM_PRE_CTRL_TPR_RESET_SEL 0x20000000
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#define BF_PRE_CTRL_TPR_RESET_SEL(v) \
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(((v) << 29) & BM_PRE_CTRL_TPR_RESET_SEL)
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#define BM_PRE_CTRL_EN_REPEAT 0x10000000
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#define BF_PRE_CTRL_EN_REPEAT(v) \
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(((v) << 28) & BM_PRE_CTRL_EN_REPEAT)
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#define BP_PRE_CTRL_RSVD2 16
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#define BM_PRE_CTRL_RSVD2 0x0FFF0000
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#define BF_PRE_CTRL_RSVD2(v) \
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(((v) << 16) & BM_PRE_CTRL_RSVD2)
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#define BP_PRE_CTRL_RSVD1 12
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#define BM_PRE_CTRL_RSVD1 0x0000F000
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#define BF_PRE_CTRL_RSVD1(v) \
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(((v) << 12) & BM_PRE_CTRL_RSVD1)
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#define BM_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN 0x00000800
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#define BF_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN(v) \
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(((v) << 11) & BM_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN)
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#define BV_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN__0 0x0
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#define BV_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN__1 0x1
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#define BP_PRE_CTRL_HANDSHAKE_LINE_NUM 9
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#define BM_PRE_CTRL_HANDSHAKE_LINE_NUM 0x00000600
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#define BF_PRE_CTRL_HANDSHAKE_LINE_NUM(v) \
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(((v) << 9) & BM_PRE_CTRL_HANDSHAKE_LINE_NUM)
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#define BV_PRE_CTRL_HANDSHAKE_LINE_NUM__0 0x0
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#define BV_PRE_CTRL_HANDSHAKE_LINE_NUM__1 0x1
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#define BV_PRE_CTRL_HANDSHAKE_LINE_NUM__2 0x2
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#define BM_PRE_CTRL_HANDSHAKE_EN 0x00000100
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#define BF_PRE_CTRL_HANDSHAKE_EN(v) \
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(((v) << 8) & BM_PRE_CTRL_HANDSHAKE_EN)
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#define BV_PRE_CTRL_HANDSHAKE_EN__0 0x0
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#define BV_PRE_CTRL_HANDSHAKE_EN__1 0x1
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#define BM_PRE_CTRL_INTERLACED_FIELD 0x00000080
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#define BF_PRE_CTRL_INTERLACED_FIELD(v) \
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(((v) << 7) & BM_PRE_CTRL_INTERLACED_FIELD)
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#define BM_PRE_CTRL_SO 0x00000040
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#define BF_PRE_CTRL_SO(v) \
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(((v) << 6) & BM_PRE_CTRL_SO)
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#define BM_PRE_CTRL_VFLIP 0x00000020
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#define BF_PRE_CTRL_VFLIP(v) \
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(((v) << 5) & BM_PRE_CTRL_VFLIP)
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#define BM_PRE_CTRL_SDW_UPDATE 0x00000010
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#define BF_PRE_CTRL_SDW_UPDATE(v) \
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(((v) << 4) & BM_PRE_CTRL_SDW_UPDATE)
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#define BM_PRE_CTRL_RSVD0 0x00000008
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#define BF_PRE_CTRL_RSVD0(v) \
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(((v) << 3) & BM_PRE_CTRL_RSVD0)
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#define BM_PRE_CTRL_BLOCK_16 0x00000004
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#define BF_PRE_CTRL_BLOCK_16(v) \
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(((v) << 2) & BM_PRE_CTRL_BLOCK_16)
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#define BV_PRE_CTRL_BLOCK_16__32x4 0x0
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#define BV_PRE_CTRL_BLOCK_16__16x4 0x1
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#define BM_PRE_CTRL_BLOCK_EN 0x00000002
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#define BF_PRE_CTRL_BLOCK_EN(v) \
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(((v) << 1) & BM_PRE_CTRL_BLOCK_EN)
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#define BV_PRE_CTRL_BLOCK_EN__0 0x0
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#define BV_PRE_CTRL_BLOCK_EN__1 0x1
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#define BM_PRE_CTRL_ENABLE 0x00000001
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#define BF_PRE_CTRL_ENABLE(v) \
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(((v) << 0) & BM_PRE_CTRL_ENABLE)
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#define HW_PRE_IRQ_MASK (0x00000010)
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#define HW_PRE_IRQ_MASK_SET (0x00000014)
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#define HW_PRE_IRQ_MASK_CLR (0x00000018)
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#define HW_PRE_IRQ_MASK_TOG (0x0000001c)
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#define BP_PRE_IRQ_MASK_RSVD1 4
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#define BM_PRE_IRQ_MASK_RSVD1 0xFFFFFFF0
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#define BF_PRE_IRQ_MASK_RSVD1(v) \
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(((v) << 4) & BM_PRE_IRQ_MASK_RSVD1)
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#define BM_PRE_IRQ_MASK_TPR_RD_NUM_BYTES_OVFL_IRQ_EN 0x00000008
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#define BF_PRE_IRQ_MASK_TPR_RD_NUM_BYTES_OVFL_IRQ_EN(v) \
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(((v) << 3) & BM_PRE_IRQ_MASK_TPR_RD_NUM_BYTES_OVFL_IRQ_EN)
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#define BM_PRE_IRQ_MASK_HANDSHAKE_ABORT_IRQ_EN 0x00000004
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#define BF_PRE_IRQ_MASK_HANDSHAKE_ABORT_IRQ_EN(v) \
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(((v) << 2) & BM_PRE_IRQ_MASK_HANDSHAKE_ABORT_IRQ_EN)
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#define BM_PRE_IRQ_MASK_STORE_IRQ_EN 0x00000002
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#define BF_PRE_IRQ_MASK_STORE_IRQ_EN(v) \
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(((v) << 1) & BM_PRE_IRQ_MASK_STORE_IRQ_EN)
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#define BM_PRE_IRQ_MASK_PREFETCH_IRQ_EN 0x00000001
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#define BF_PRE_IRQ_MASK_PREFETCH_IRQ_EN(v) \
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(((v) << 0) & BM_PRE_IRQ_MASK_PREFETCH_IRQ_EN)
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#define HW_PRE_IRQ (0x00000020)
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#define HW_PRE_IRQ_SET (0x00000024)
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#define HW_PRE_IRQ_CLR (0x00000028)
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#define HW_PRE_IRQ_TOG (0x0000002c)
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#define BP_PRE_IRQ_RSVD1 14
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#define BM_PRE_IRQ_RSVD1 0xFFFFC000
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#define BF_PRE_IRQ_RSVD1(v) \
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(((v) << 14) & BM_PRE_IRQ_RSVD1)
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#define BP_PRE_IRQ_AXI_ERROR_ID 10
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#define BM_PRE_IRQ_AXI_ERROR_ID 0x00003C00
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#define BF_PRE_IRQ_AXI_ERROR_ID(v) \
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(((v) << 10) & BM_PRE_IRQ_AXI_ERROR_ID)
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#define BM_PRE_IRQ_AXI_READ_ERROR 0x00000200
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#define BF_PRE_IRQ_AXI_READ_ERROR(v) \
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(((v) << 9) & BM_PRE_IRQ_AXI_READ_ERROR)
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#define BM_PRE_IRQ_AXI_WRITE_ERROR 0x00000100
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#define BF_PRE_IRQ_AXI_WRITE_ERROR(v) \
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(((v) << 8) & BM_PRE_IRQ_AXI_WRITE_ERROR)
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#define BP_PRE_IRQ_RSVD0 5
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#define BM_PRE_IRQ_RSVD0 0x000000E0
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#define BF_PRE_IRQ_RSVD0(v) \
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(((v) << 5) & BM_PRE_IRQ_RSVD0)
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#define BM_PRE_IRQ_HANDSHAKE_ERROR_IRQ 0x00000010
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#define BF_PRE_IRQ_HANDSHAKE_ERROR_IRQ(v) \
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(((v) << 4) & BM_PRE_IRQ_HANDSHAKE_ERROR_IRQ)
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#define BM_PRE_IRQ_TPR_RD_NUM_BYTES_OVFL_IRQ 0x00000008
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#define BF_PRE_IRQ_TPR_RD_NUM_BYTES_OVFL_IRQ(v) \
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(((v) << 3) & BM_PRE_IRQ_TPR_RD_NUM_BYTES_OVFL_IRQ)
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#define BM_PRE_IRQ_HANDSHAKE_ABORT_IRQ 0x00000004
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#define BF_PRE_IRQ_HANDSHAKE_ABORT_IRQ(v) \
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(((v) << 2) & BM_PRE_IRQ_HANDSHAKE_ABORT_IRQ)
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#define BM_PRE_IRQ_STORE_IRQ 0x00000002
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#define BF_PRE_IRQ_STORE_IRQ(v) \
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(((v) << 1) & BM_PRE_IRQ_STORE_IRQ)
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#define BM_PRE_IRQ_PREFETCH_IRQ 0x00000001
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#define BF_PRE_IRQ_PREFETCH_IRQ(v) \
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(((v) << 0) & BM_PRE_IRQ_PREFETCH_IRQ)
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#define HW_PRE_CUR_BUF (0x00000030)
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#define BP_PRE_CUR_BUF_ADDR 0
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#define BM_PRE_CUR_BUF_ADDR 0xFFFFFFFF
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#define BF_PRE_CUR_BUF_ADDR(v) (v)
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#define HW_PRE_NEXT_BUF (0x00000040)
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#define BP_PRE_NEXT_BUF_ADDR 0
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#define BM_PRE_NEXT_BUF_ADDR 0xFFFFFFFF
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#define BF_PRE_NEXT_BUF_ADDR(v) (v)
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#define HW_PRE_U_BUF_OFFSET (0x00000050)
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#define BP_PRE_U_BUF_OFFSET_RSVD0 25
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#define BM_PRE_U_BUF_OFFSET_RSVD0 0xFE000000
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#define BF_PRE_U_BUF_OFFSET_RSVD0(v) \
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(((v) << 25) & BM_PRE_U_BUF_OFFSET_RSVD0)
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#define BP_PRE_U_BUF_OFFSET_UBO 0
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#define BM_PRE_U_BUF_OFFSET_UBO 0x01FFFFFF
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#define BF_PRE_U_BUF_OFFSET_UBO(v) \
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(((v) << 0) & BM_PRE_U_BUF_OFFSET_UBO)
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#define HW_PRE_V_BUF_OFFSET (0x00000060)
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#define BP_PRE_V_BUF_OFFSET_RSVD0 25
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#define BM_PRE_V_BUF_OFFSET_RSVD0 0xFE000000
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#define BF_PRE_V_BUF_OFFSET_RSVD0(v) \
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(((v) << 25) & BM_PRE_V_BUF_OFFSET_RSVD0)
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#define BP_PRE_V_BUF_OFFSET_VBO 0
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#define BM_PRE_V_BUF_OFFSET_VBO 0x01FFFFFF
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#define BF_PRE_V_BUF_OFFSET_VBO(v) \
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(((v) << 0) & BM_PRE_V_BUF_OFFSET_VBO)
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#define HW_PRE_TPR_CTRL (0x00000070)
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#define HW_PRE_TPR_CTRL_SET (0x00000074)
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#define HW_PRE_TPR_CTRL_CLR (0x00000078)
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#define HW_PRE_TPR_CTRL_TOG (0x0000007c)
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#define BP_PRE_TPR_CTRL_RSVD 8
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#define BM_PRE_TPR_CTRL_RSVD 0xFFFFFF00
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#define BF_PRE_TPR_CTRL_RSVD(v) \
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(((v) << 8) & BM_PRE_TPR_CTRL_RSVD)
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#define BP_PRE_TPR_CTRL_TILE_FORMAT 0
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#define BM_PRE_TPR_CTRL_TILE_FORMAT 0x000000FF
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#define BF_PRE_TPR_CTRL_TILE_FORMAT(v) \
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(((v) << 0) & BM_PRE_TPR_CTRL_TILE_FORMAT)
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__BYPASS 0x00
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_SB_ST 0x10
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_SB_SRT 0x50
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_ST 0x20
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_SRT 0x60
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_MST 0xA0
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU32_MSRT 0xE0
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_SB_ST 0x11
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_SB_SRT 0x51
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_ST 0x21
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_SRT 0x61
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_MST 0xA1
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__GPU16_MSRT 0xE1
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__VPU8_PRO 0x22
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#define BV_PRE_TPR_CTRL_TILE_FORMAT__VPU8_SB_INT 0x13
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#define HW_PRE_PREFETCH_ENGINE_CTRL (0x00000080)
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#define HW_PRE_PREFETCH_ENGINE_CTRL_SET (0x00000084)
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#define HW_PRE_PREFETCH_ENGINE_CTRL_CLR (0x00000088)
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#define HW_PRE_PREFETCH_ENGINE_CTRL_TOG (0x0000008c)
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#define BP_PRE_PREFETCH_ENGINE_CTRL_RSVD1 16
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#define BM_PRE_PREFETCH_ENGINE_CTRL_RSVD1 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_CTRL_RSVD1(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_CTRL_RSVD1)
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#define BM_PRE_PREFETCH_ENGINE_CTRL_TPR_COOR_OFFSET_EN 0x00008000
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#define BF_PRE_PREFETCH_ENGINE_CTRL_TPR_COOR_OFFSET_EN(v) \
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(((v) << 15) & BM_PRE_PREFETCH_ENGINE_CTRL_TPR_COOR_OFFSET_EN)
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#define BM_PRE_PREFETCH_ENGINE_CTRL_PARTIAL_UV_SWAP 0x00004000
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#define BF_PRE_PREFETCH_ENGINE_CTRL_PARTIAL_UV_SWAP(v) \
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(((v) << 14) & BM_PRE_PREFETCH_ENGINE_CTRL_PARTIAL_UV_SWAP)
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#define BM_PRE_PREFETCH_ENGINE_CTRL_CROP_EN 0x00002000
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#define BF_PRE_PREFETCH_ENGINE_CTRL_CROP_EN(v) \
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(((v) << 13) & BM_PRE_PREFETCH_ENGINE_CTRL_CROP_EN)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_CROP_EN__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_CROP_EN__1 0x1
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#define BM_PRE_PREFETCH_ENGINE_CTRL_FIELD_INVERSE 0x00001000
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#define BF_PRE_PREFETCH_ENGINE_CTRL_FIELD_INVERSE(v) \
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(((v) << 12) & BM_PRE_PREFETCH_ENGINE_CTRL_FIELD_INVERSE)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_FIELD_INVERSE__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_FIELD_INVERSE__1 0x1
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#define BM_PRE_PREFETCH_ENGINE_CTRL_SHIFT_BYPASS 0x00000800
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#define BF_PRE_PREFETCH_ENGINE_CTRL_SHIFT_BYPASS(v) \
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(((v) << 11) & BM_PRE_PREFETCH_ENGINE_CTRL_SHIFT_BYPASS)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_SHIFT_BYPASS__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_SHIFT_BYPASS__1 0x1
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#define BP_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT 8
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#define BM_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT 0x00000700
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#define BF_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT(v) \
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(((v) << 8) & BM_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__1 0x1
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__2 0x2
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__3 0x3
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__4 0x4
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_PIXEL_FORMAT__5 0x5
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#define BP_PRE_PREFETCH_ENGINE_CTRL_RSVD0 6
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#define BM_PRE_PREFETCH_ENGINE_CTRL_RSVD0 0x000000C0
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#define BF_PRE_PREFETCH_ENGINE_CTRL_RSVD0(v) \
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(((v) << 6) & BM_PRE_PREFETCH_ENGINE_CTRL_RSVD0)
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#define BP_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP 4
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#define BM_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP 0x00000030
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#define BF_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP(v) \
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(((v) << 4) & BM_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP__1 0x1
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP__2 0x2
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#define BV_PRE_PREFETCH_ENGINE_CTRL_INPUT_ACTIVE_BPP__3 0x3
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#define BP_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES 1
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#define BM_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES 0x0000000E
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#define BF_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES(v) \
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(((v) << 1) & BM_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES__8_bytes 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES__16_bytes 0x1
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#define BV_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES__32_bytes 0x2
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#define BV_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES__64_bytes 0x3
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#define BV_PRE_PREFETCH_ENGINE_CTRL_RD_NUM_BYTES__128_bytes 0x4
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#define BM_PRE_PREFETCH_ENGINE_CTRL_PREFETCH_EN 0x00000001
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#define BF_PRE_PREFETCH_ENGINE_CTRL_PREFETCH_EN(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_CTRL_PREFETCH_EN)
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#define BV_PRE_PREFETCH_ENGINE_CTRL_PREFETCH_EN__0 0x0
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#define BV_PRE_PREFETCH_ENGINE_CTRL_PREFETCH_EN__1 0x1
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#define HW_PRE_PREFETCH_ENGINE_STATUS (0x00000090)
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#define BP_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_Y 16
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#define BM_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_Y 0x3FFF0000
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#define BF_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_Y(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_Y)
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#define BP_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_X 0
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#define BM_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_X 0x0000FFFF
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#define BF_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_X(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_STATUS_PREFETCH_BLOCK_X)
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#define HW_PRE_PREFETCH_ENGINE_INPUT_SIZE (0x000000a0)
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#define BP_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_HEIGHT 16
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#define BM_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_HEIGHT 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_HEIGHT(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_HEIGHT)
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#define BP_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_WIDTH 0
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#define BM_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_WIDTH 0x0000FFFF
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#define BF_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_WIDTH(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_INPUT_SIZE_INPUT_WIDTH)
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#define HW_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC (0x000000b0)
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#define BP_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_Y 16
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#define BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_Y 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_Y(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_Y)
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#define BP_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_X 0
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#define BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_X 0x0000FFFF
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#define BF_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_X(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_ULC_OUTPUT_SIZE_ULC_X)
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#define HW_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC (0x000000c0)
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#define BP_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_Y 16
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#define BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_Y 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_Y(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_Y)
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#define BP_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_X 0
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#define BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_X 0x0000FFFF
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#define BF_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_X(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_OUTPUT_SIZE_LRC_OUTPUT_SIZE_LRC_X)
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#define HW_PRE_PREFETCH_ENGINE_PITCH (0x000000d0)
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#define BP_PRE_PREFETCH_ENGINE_PITCH_INPUT_UV_PITCH 16
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#define BM_PRE_PREFETCH_ENGINE_PITCH_INPUT_UV_PITCH 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_PITCH_INPUT_UV_PITCH(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_PITCH_INPUT_UV_PITCH)
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#define BP_PRE_PREFETCH_ENGINE_PITCH_INPUT_Y_PITCH 0
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#define BM_PRE_PREFETCH_ENGINE_PITCH_INPUT_Y_PITCH 0x0000FFFF
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#define BF_PRE_PREFETCH_ENGINE_PITCH_INPUT_Y_PITCH(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_PITCH_INPUT_Y_PITCH)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_OFFSET (0x000000e0)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_SET (0x000000e4)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_CLR (0x000000e8)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_TOG (0x000000ec)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD0 29
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD0 0xE0000000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD0(v) \
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(((v) << 29) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD0)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET3 24
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET3 0x1F000000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET3(v) \
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(((v) << 24) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET3)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD1 21
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD1 0x00E00000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD1(v) \
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(((v) << 21) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD1)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET2 16
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET2 0x001F0000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET2(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET2)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD2 13
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD2 0x0000E000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD2(v) \
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(((v) << 13) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD2)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET1 8
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET1 0x00001F00
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET1(v) \
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(((v) << 8) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET1)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD3 5
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD3 0x000000E0
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD3(v) \
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(((v) << 5) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_RSVD3)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET0 0
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET0 0x0000001F
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET0(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_SHIFT_OFFSET_OFFSET0)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_WIDTH (0x000000f0)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_SET (0x000000f4)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_CLR (0x000000f8)
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#define HW_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_TOG (0x000000fc)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_RSVD0 16
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_RSVD0 0xFFFF0000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_RSVD0(v) \
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(((v) << 16) & BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_RSVD0)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH3 12
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH3 0x0000F000
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH3(v) \
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(((v) << 12) & BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH3)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH2 8
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH2 0x00000F00
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH2(v) \
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(((v) << 8) & BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH2)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH1 4
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH1 0x000000F0
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH1(v) \
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(((v) << 4) & BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH1)
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#define BP_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH0 0
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#define BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH0 0x0000000F
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#define BF_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH0(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_SHIFT_WIDTH_WIDTH0)
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#define HW_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET (0x00000100)
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#define BP_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_RSVD0 23
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#define BM_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_RSVD0 0xFF800000
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#define BF_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_RSVD0(v) \
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(((v) << 23) & BM_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_RSVD0)
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#define BP_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_INTERLACE_OFFSET 0
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#define BM_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_INTERLACE_OFFSET 0xFFFFFFFF
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#define BF_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_INTERLACE_OFFSET(v) \
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(((v) << 0) & BM_PRE_PREFETCH_ENGINE_INTERLACE_OFFSET_INTERLACE_OFFSET)
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#define HW_PRE_STORE_ENGINE_CTRL (0x00000110)
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#define HW_PRE_STORE_ENGINE_CTRL_SET (0x00000114)
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#define HW_PRE_STORE_ENGINE_CTRL_CLR (0x00000118)
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#define HW_PRE_STORE_ENGINE_CTRL_TOG (0x0000011c)
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#define BP_PRE_STORE_ENGINE_CTRL_RSVD0 6
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#define BM_PRE_STORE_ENGINE_CTRL_RSVD0 0xFFFFFFC0
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#define BF_PRE_STORE_ENGINE_CTRL_RSVD0(v) \
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(((v) << 6) & BM_PRE_STORE_ENGINE_CTRL_RSVD0)
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#define BP_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP 4
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#define BM_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP 0x00000030
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#define BF_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP(v) \
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(((v) << 4) & BM_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP)
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#define BV_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP__8_bits 0x0
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#define BV_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP__16_bits 0x1
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#define BV_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP__32_bits 0x2
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#define BV_PRE_STORE_ENGINE_CTRL_OUTPUT_ACTIVE_BPP__64_bits 0x3
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#define BP_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES 1
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#define BM_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES 0x0000000E
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#define BF_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES(v) \
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(((v) << 1) & BM_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES)
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#define BV_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES__8_bytes 0x0
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#define BV_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES__16_bytes 0x1
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#define BV_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES__32_bytes 0x2
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#define BV_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES__64_bytes 0x3
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#define BV_PRE_STORE_ENGINE_CTRL_WR_NUM_BYTES__128_bytes 0x4
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#define BM_PRE_STORE_ENGINE_CTRL_STORE_EN 0x00000001
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#define BF_PRE_STORE_ENGINE_CTRL_STORE_EN(v) \
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(((v) << 0) & BM_PRE_STORE_ENGINE_CTRL_STORE_EN)
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#define BV_PRE_STORE_ENGINE_CTRL_STORE_EN__0 0x0
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#define BV_PRE_STORE_ENGINE_CTRL_STORE_EN__1 0x1
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#define HW_PRE_STORE_ENGINE_STATUS (0x00000120)
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#define BP_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_Y 16
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#define BM_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_Y 0x3FFF0000
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#define BF_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_Y(v) \
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(((v) << 16) & BM_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_Y)
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#define BP_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_X 0
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#define BM_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_X 0x0000FFFF
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#define BF_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_X(v) \
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(((v) << 0) & BM_PRE_STORE_ENGINE_STATUS_STORE_BLOCK_X)
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#define HW_PRE_STORE_ENGINE_SIZE (0x00000130)
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#define BP_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_HEIGHT 16
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#define BM_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_HEIGHT 0xFFFF0000
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#define BF_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_HEIGHT(v) \
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(((v) << 16) & BM_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_HEIGHT)
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#define BP_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_WIDTH 0
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#define BM_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_WIDTH 0x0000FFFF
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#define BF_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_WIDTH(v) \
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(((v) << 0) & BM_PRE_STORE_ENGINE_SIZE_INPUT_TOTAL_WIDTH)
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#define HW_PRE_STORE_ENGINE_PITCH (0x00000140)
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#define BP_PRE_STORE_ENGINE_PITCH_RSVD0 16
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#define BM_PRE_STORE_ENGINE_PITCH_RSVD0 0xFFFF0000
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#define BF_PRE_STORE_ENGINE_PITCH_RSVD0(v) \
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(((v) << 16) & BM_PRE_STORE_ENGINE_PITCH_RSVD0)
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#define BP_PRE_STORE_ENGINE_PITCH_OUT_PITCH 0
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#define BM_PRE_STORE_ENGINE_PITCH_OUT_PITCH 0x0000FFFF
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#define BF_PRE_STORE_ENGINE_PITCH_OUT_PITCH(v) \
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(((v) << 0) & BM_PRE_STORE_ENGINE_PITCH_OUT_PITCH)
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#define HW_PRE_STORE_ENGINE_ADDR (0x00000150)
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#define BP_PRE_STORE_ENGINE_ADDR_OUT_BASE_ADDR 0
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#define BM_PRE_STORE_ENGINE_ADDR_OUT_BASE_ADDR 0xFFFFFFFF
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#define BF_PRE_STORE_ENGINE_ADDR_OUT_BASE_ADDR(v) (v)
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#endif /* __ARCH_ARM___PRE_H */
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