![Sathya Perla](/assets/img/avatar_default.png)
Here's a patch tp remove the subdirectories in staging/benet (1st item in staging/benet/TODO). Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
183 lines
5.4 KiB
C
183 lines
5.4 KiB
C
/*
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* Copyright (C) 2005 - 2008 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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/*
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* Autogenerated by srcgen version: 0127
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*/
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#ifndef __host_struct_amap_h__
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#define __host_struct_amap_h__
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#include "be_cm.h"
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#include "be_common.h"
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#include "descriptors.h"
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/* --- EQ_COMPLETION_MAJOR_CODE_ENUM --- */
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#define EQ_MAJOR_CODE_COMPLETION (0) /* Completion event on a */
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/* qcompletion ueue. */
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#define EQ_MAJOR_CODE_ETH (1) /* Affiliated Ethernet Event. */
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#define EQ_MAJOR_CODE_RESERVED (2) /* Reserved */
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#define EQ_MAJOR_CODE_RDMA (3) /* Affiliated RDMA Event. */
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#define EQ_MAJOR_CODE_ISCSI (4) /* Affiliated ISCSI Event */
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#define EQ_MAJOR_CODE_UNAFFILIATED (5) /* Unaffiliated Event */
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/* --- EQ_COMPLETION_MINOR_CODE_ENUM --- */
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#define EQ_MINOR_CODE_COMPLETION (0) /* Completion event on a */
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/* completion queue. */
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#define EQ_MINOR_CODE_OTHER (1) /* Other Event (TBD). */
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/* Queue Entry Definition for all 4 byte event queue types. */
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struct BE_EQ_ENTRY_AMAP {
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u8 Valid; /* DWORD 0 */
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u8 MajorCode[3]; /* DWORD 0 */
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u8 MinorCode[12]; /* DWORD 0 */
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u8 ResourceID[16]; /* DWORD 0 */
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} __packed;
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struct EQ_ENTRY_AMAP {
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u32 dw[1];
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};
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/*
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* --- ETH_EVENT_CODE ---
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* These codes are returned by the MPU when one of these events has occurred,
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* and the event is configured to report to an Event Queue when an event
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* is detected.
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*/
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#define ETH_EQ_LINK_STATUS (0) /* Link status change event */
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/* detected. */
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#define ETH_EQ_WATERMARK (1) /* watermark event detected. */
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#define ETH_EQ_MAGIC_PKT (2) /* magic pkt event detected. */
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#define ETH_EQ_ACPI_PKT0 (3) /* ACPI interesting packet */
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/* detected. */
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#define ETH_EQ_ACPI_PKT1 (3) /* ACPI interesting packet */
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/* detected. */
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#define ETH_EQ_ACPI_PKT2 (3) /* ACPI interesting packet */
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/* detected. */
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#define ETH_EQ_ACPI_PKT3 (3) /* ACPI interesting packet */
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/* detected. */
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/*
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* --- ETH_TX_COMPL_STATUS_ENUM ---
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* Status codes contained in Ethernet TX completion descriptors.
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*/
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#define ETH_COMP_VALID (0)
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#define ETH_COMP_ERROR (1)
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#define ETH_COMP_INVALID (15)
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/*
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* --- ETH_TX_COMPL_PORT_ENUM ---
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* Port indicator contained in Ethernet TX completion descriptors.
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*/
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#define ETH_COMP_PORT0 (0)
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#define ETH_COMP_PORT1 (1)
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#define ETH_COMP_MGMT (2)
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/*
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* --- ETH_TX_COMPL_CT_ENUM ---
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* Completion type indicator contained in Ethernet TX completion descriptors.
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*/
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#define ETH_COMP_ETH (0)
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/*
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* Work request block that the driver issues to the chip for
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* Ethernet transmissions. All control fields must be valid in each WRB for
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* a message. The controller, as specified by the flags, optionally writes
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* an entry to the Completion Ring and generate an event.
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*/
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struct BE_ETH_WRB_AMAP {
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u8 frag_pa_hi[32]; /* DWORD 0 */
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u8 frag_pa_lo[32]; /* DWORD 1 */
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u8 complete; /* DWORD 2 */
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u8 event; /* DWORD 2 */
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u8 crc; /* DWORD 2 */
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u8 forward; /* DWORD 2 */
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u8 ipsec; /* DWORD 2 */
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u8 mgmt; /* DWORD 2 */
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u8 ipcs; /* DWORD 2 */
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u8 udpcs; /* DWORD 2 */
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u8 tcpcs; /* DWORD 2 */
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u8 lso; /* DWORD 2 */
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u8 last; /* DWORD 2 */
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u8 vlan; /* DWORD 2 */
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u8 dbg[3]; /* DWORD 2 */
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u8 hash_val[3]; /* DWORD 2 */
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u8 lso_mss[14]; /* DWORD 2 */
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u8 frag_len[16]; /* DWORD 3 */
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u8 vlan_tag[16]; /* DWORD 3 */
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} __packed;
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struct ETH_WRB_AMAP {
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u32 dw[4];
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};
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/* This is an Ethernet transmit completion descriptor */
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struct BE_ETH_TX_COMPL_AMAP {
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u8 user_bytes[16]; /* DWORD 0 */
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u8 nwh_bytes[8]; /* DWORD 0 */
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u8 lso; /* DWORD 0 */
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u8 rsvd0[7]; /* DWORD 0 */
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u8 wrb_index[16]; /* DWORD 1 */
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u8 ct[2]; /* DWORD 1 */
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u8 port[2]; /* DWORD 1 */
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u8 rsvd1[8]; /* DWORD 1 */
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u8 status[4]; /* DWORD 1 */
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u8 rsvd2[16]; /* DWORD 2 */
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u8 ringid[11]; /* DWORD 2 */
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u8 hash_val[4]; /* DWORD 2 */
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u8 valid; /* DWORD 2 */
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u8 rsvd3[32]; /* DWORD 3 */
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} __packed;
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struct ETH_TX_COMPL_AMAP {
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u32 dw[4];
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};
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/* Ethernet Receive Buffer descriptor */
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struct BE_ETH_RX_D_AMAP {
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u8 fragpa_hi[32]; /* DWORD 0 */
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u8 fragpa_lo[32]; /* DWORD 1 */
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} __packed;
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struct ETH_RX_D_AMAP {
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u32 dw[2];
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};
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/* This is an Ethernet Receive Completion Descriptor */
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struct BE_ETH_RX_COMPL_AMAP {
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u8 vlan_tag[16]; /* DWORD 0 */
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u8 pktsize[14]; /* DWORD 0 */
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u8 port; /* DWORD 0 */
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u8 rsvd0; /* DWORD 0 */
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u8 err; /* DWORD 1 */
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u8 rsshp; /* DWORD 1 */
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u8 ipf; /* DWORD 1 */
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u8 tcpf; /* DWORD 1 */
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u8 udpf; /* DWORD 1 */
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u8 ipcksm; /* DWORD 1 */
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u8 tcpcksm; /* DWORD 1 */
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u8 udpcksm; /* DWORD 1 */
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u8 macdst[6]; /* DWORD 1 */
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u8 vtp; /* DWORD 1 */
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u8 vtm; /* DWORD 1 */
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u8 fragndx[10]; /* DWORD 1 */
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u8 ct[2]; /* DWORD 1 */
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u8 ipsec; /* DWORD 1 */
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u8 numfrags[3]; /* DWORD 1 */
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u8 rsvd1[31]; /* DWORD 2 */
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u8 valid; /* DWORD 2 */
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u8 rsshash[32]; /* DWORD 3 */
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} __packed;
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struct ETH_RX_COMPL_AMAP {
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u32 dw[4];
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};
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#endif /* __host_struct_amap_h__ */
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