![Dan Carpenter](/assets/img/avatar_default.png)
Bitwise OR was clearly intended here. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
636 lines
18 KiB
C
636 lines
18 KiB
C
/*
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* SBE 2T3E3 synchronous serial card driver for Linux
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*
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* Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This code is based on a driver written by SBE Inc.
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*/
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#include <linux/hdlc.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include "2t3e3.h"
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irqreturn_t t3e3_intr(int irq, void *dev_instance)
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{
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struct channel *sc = dev_to_priv(dev_instance);
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u32 val;
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irqreturn_t ret = IRQ_NONE;
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sc->interrupt_active = 1;
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val = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR);
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if (val & SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_CHANGE) {
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dev_dbg(&sc->pdev->dev,
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"Rx LOS Chng Int r=%02x (LOS|OOF=%02x)\n",
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val, (sc->s.LOS << 4) | sc->s.OOF);
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cpld_LOS_update(sc);
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ret = IRQ_HANDLED;
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}
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if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ASSERTED) {
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dc_intr(sc);
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ret = IRQ_HANDLED;
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}
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if (val & SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ASSERTED) {
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exar7250_intr(sc);
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ret = IRQ_HANDLED;
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}
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/*
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we don't care about other interrupt sources (DMO, LOS, LCV) because
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they are handled by Framer too
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*/
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sc->interrupt_active = 0;
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return ret;
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}
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void dc_intr(struct channel *sc)
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{
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u32 val;
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/* disable ethernet interrupts */
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/* grrr this clears interrupt summary bits !!! */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
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while ((val = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS)) &
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(SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED |
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SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
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SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
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SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW |
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SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED |
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SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)) {
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dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, val);
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dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Ethernet controller interrupt! (CSR5 = %08X)\n",
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val);
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if (val & (SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT |
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SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE |
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SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)) {
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if (val & SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT)
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dev_dbg(&sc->pdev->dev,
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"Receive interrupt (LOS=%d, OOF=%d)\n",
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sc->s.LOS, sc->s.OOF);
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if (val & SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE)
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dev_dbg(&sc->pdev->dev,
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"Receive buffer unavailable\n");
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if (val & SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STOPPED)
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dev_dbg(&sc->pdev->dev,
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"Receive process stopped\n");
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dc_intr_rx(sc);
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}
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if (val & SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW) {
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dev_dbg(&sc->pdev->dev, "Transmit underflow\n");
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dc_intr_tx_underflow(sc);
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}
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if (val & (SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE |
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SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT |
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SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)) {
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if (val & SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT)
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dev_dbg(&sc->pdev->dev, "Transmit interrupt\n");
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if (val & SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE)
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dev_dbg(&sc->pdev->dev,
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"Transmit buffer unavailable\n");
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if (val & SBE_2T3E3_21143_VAL_TRANSMIT_PROCESS_STOPPED)
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dev_dbg(&sc->pdev->dev,
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"Transmit process stopped\n");
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dc_intr_tx(sc);
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}
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}
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/* enable ethernet interrupts */
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dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
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sc->ether.interrupt_enable_mask);
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}
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void dc_intr_rx(struct channel *sc)
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{
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u32 current_read;
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u32 error_mask, error;
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t3e3_rx_desc_t *current_desc;
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struct sk_buff *m, *m2;
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unsigned rcv_len;
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sc->rcv_count++; /* for the activity LED */
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current_read = sc->ether.rx_ring_current_read;
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dev_dbg(&sc->pdev->dev, "intr_rx current_read = %d\n", current_read);
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/* when ethernet loopback is set, ignore framer signals */
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if ((sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) && sc->s.OOF) {
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while (!(sc->ether.rx_ring[current_read].rdes0 &
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SBE_2T3E3_RX_DESC_21143_OWN)) {
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current_desc = &sc->ether.rx_ring[current_read];
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current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
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SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
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current_desc->rdes1 |= SBE_2T3E3_MTU;
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current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
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current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
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}
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sc->ether.rx_ring_current_read = current_read;
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return;
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}
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while (!(sc->ether.rx_ring[current_read].rdes0 &
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SBE_2T3E3_RX_DESC_21143_OWN)) {
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current_desc = &sc->ether.rx_ring[current_read];
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dev_dbg(&sc->pdev->dev, "rdes0: %08X rdes1: %08X\n",
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current_desc->rdes0, current_desc->rdes1);
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m = sc->ether.rx_data[current_read];
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rcv_len = (current_desc->rdes0 & SBE_2T3E3_RX_DESC_FRAME_LENGTH) >>
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SBE_2T3E3_RX_DESC_FRAME_LENGTH_SHIFT;
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dev_dbg(&sc->pdev->dev, "mbuf was received (mbuf len = %d)\n",
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rcv_len);
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switch (sc->p.crc) {
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case SBE_2T3E3_CRC_16:
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rcv_len -= SBE_2T3E3_CRC16_LENGTH;
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break;
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case SBE_2T3E3_CRC_32:
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rcv_len -= SBE_2T3E3_CRC32_LENGTH;
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break;
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default:
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break;
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}
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if (current_desc->rdes0 & SBE_2T3E3_RX_DESC_LAST_DESC) {
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/* TODO: is collision possible? */
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error_mask = SBE_2T3E3_RX_DESC_DESC_ERROR |
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SBE_2T3E3_RX_DESC_COLLISION_SEEN |
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SBE_2T3E3_RX_DESC_DRIBBLING_BIT;
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switch (sc->p.frame_mode) {
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case SBE_2T3E3_FRAME_MODE_HDLC:
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error_mask |= SBE_2T3E3_RX_DESC_MII_ERROR;
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if (sc->p.crc == SBE_2T3E3_CRC_32)
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error_mask |= SBE_2T3E3_RX_DESC_CRC_ERROR;
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break;
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case SBE_2T3E3_FRAME_MODE_TRANSPARENT:
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case SBE_2T3E3_FRAME_MODE_RAW:
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break;
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default:
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error_mask = 0;
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}
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if (sc->s.LOS) {
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error_mask &= ~(SBE_2T3E3_RX_DESC_DRIBBLING_BIT |
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SBE_2T3E3_RX_DESC_MII_ERROR);
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}
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error = current_desc->rdes0 & error_mask;
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if (error) {
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sc->s.in_errors++;
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dev_dbg(&sc->pdev->dev,
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"error interrupt: NO_ERROR_MESSAGE = %d\n",
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sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES ? 1 : 0);
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current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
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SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
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current_desc->rdes1 |= SBE_2T3E3_MTU;
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current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
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if (error & SBE_2T3E3_RX_DESC_DESC_ERROR) {
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev,
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"SBE 2T3E3: descriptor error\n");
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sc->s.in_error_desc++;
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}
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if (error & SBE_2T3E3_RX_DESC_COLLISION_SEEN) {
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev,
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"SBE 2T3E3: collision seen\n");
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sc->s.in_error_coll++;
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} else {
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if (error & SBE_2T3E3_RX_DESC_DRIBBLING_BIT) {
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev,
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"SBE 2T3E3: dribbling bits error\n");
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sc->s.in_error_drib++;
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}
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if (error & SBE_2T3E3_RX_DESC_CRC_ERROR) {
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev,
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"SBE 2T3E3: crc error\n");
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sc->s.in_error_crc++;
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}
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}
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if (error & SBE_2T3E3_RX_DESC_MII_ERROR) {
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev, "SBE 2T3E3: mii error\n");
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sc->s.in_error_mii++;
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}
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current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
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sc->r.flags |= SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
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continue;
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}
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}
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current_desc->rdes1 &= SBE_2T3E3_RX_DESC_END_OF_RING |
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SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED;
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current_desc->rdes1 |= SBE_2T3E3_MTU;
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if (rcv_len > 1600) {
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sc->s.in_errors++;
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sc->s.in_dropped++;
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if (!(sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES))
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dev_err(&sc->pdev->dev, "SBE 2T3E3: oversized rx: rdes0 = %08X\n",
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current_desc->rdes0);
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} else {
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m2 = dev_alloc_skb(MCLBYTES);
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if (m2 != NULL) {
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current_desc->rdes2 = virt_to_phys(m2->data);
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sc->ether.rx_data[current_read] = m2;
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sc->s.in_packets++;
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sc->s.in_bytes += rcv_len;
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m->dev = sc->dev;
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skb_put(m, rcv_len);
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skb_reset_mac_header(m);
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m->protocol = hdlc_type_trans(m, m->dev);
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netif_rx(m);
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/* good packet was received so we will show error messages again... */
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if (sc->r.flags & SBE_2T3E3_FLAG_NO_ERROR_MESSAGES) {
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dev_dbg(&sc->pdev->dev,
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"setting ERROR_MESSAGES->0\n");
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sc->r.flags &= ~SBE_2T3E3_FLAG_NO_ERROR_MESSAGES;
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}
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} else {
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sc->s.in_errors++;
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sc->s.in_dropped++;
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}
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}
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current_desc->rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
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current_read = (current_read + 1) % SBE_2T3E3_RX_DESC_RING_SIZE;
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}
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sc->ether.rx_ring_current_read = current_read;
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dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
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}
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void dc_intr_tx(struct channel *sc)
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{
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u32 current_read, current_write;
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u32 last_segment, error;
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t3e3_tx_desc_t *current_desc;
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spin_lock(&sc->ether.tx_lock);
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current_read = sc->ether.tx_ring_current_read;
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current_write = sc->ether.tx_ring_current_write;
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while (current_read != current_write) {
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current_desc = &sc->ether.tx_ring[current_read];
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if (current_desc->tdes0 & SBE_2T3E3_RX_DESC_21143_OWN)
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break;
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dev_dbg(&sc->pdev->dev,
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"txeof: tdes0 = %08X tdes1 = %08X\n",
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current_desc->tdes0, current_desc->tdes1);
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error = current_desc->tdes0 & (SBE_2T3E3_TX_DESC_ERROR_SUMMARY |
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SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT |
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SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER |
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SBE_2T3E3_TX_DESC_NO_CARRIER |
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SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT |
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SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR |
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SBE_2T3E3_TX_DESC_DEFFERED);
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last_segment = current_desc->tdes1 & SBE_2T3E3_TX_DESC_LAST_SEGMENT;
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current_desc->tdes0 = 0;
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current_desc->tdes1 &= SBE_2T3E3_TX_DESC_END_OF_RING |
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SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED;
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current_desc->tdes2 = 0;
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sc->ether.tx_free_cnt++;
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if (last_segment != SBE_2T3E3_TX_DESC_LAST_SEGMENT) {
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current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
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continue;
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}
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if (sc->ether.tx_data[current_read]) {
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sc->s.out_packets++;
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sc->s.out_bytes += sc->ether.tx_data[current_read]->len;
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dev_kfree_skb_any(sc->ether.tx_data[current_read]);
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sc->ether.tx_data[current_read] = NULL;
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}
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if (error > 0) {
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sc->s.out_errors++;
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if (error & SBE_2T3E3_TX_DESC_TRANSMIT_JABBER_TIMEOUT) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: transmit jabber timeout\n");
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sc->s.out_error_jab++;
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}
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if (sc->p.loopback != SBE_2T3E3_LOOPBACK_ETHERNET) {
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if (error & SBE_2T3E3_TX_DESC_LOSS_OF_CARRIER) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: loss of carrier\n");
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sc->s.out_error_lost_carr++;
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}
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if (error & SBE_2T3E3_TX_DESC_NO_CARRIER) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: no carrier\n");
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sc->s.out_error_no_carr++;
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}
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}
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if (error & SBE_2T3E3_TX_DESC_LINK_FAIL_REPORT) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: link fail report\n");
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sc->s.out_error_link_fail++;
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}
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if (error & SBE_2T3E3_TX_DESC_UNDERFLOW_ERROR) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3:"
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" transmission underflow error\n");
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sc->s.out_error_underflow++;
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spin_unlock(&sc->ether.tx_lock);
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dc_restart(sc);
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return;
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}
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if (error & SBE_2T3E3_TX_DESC_DEFFERED) {
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dev_err(&sc->pdev->dev, "SBE 2T3E3: transmission deferred\n");
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sc->s.out_error_dereferred++;
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}
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}
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current_read = (current_read + 1) % SBE_2T3E3_TX_DESC_RING_SIZE;
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}
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sc->ether.tx_ring_current_read = current_read;
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/* Relieve flow control when the TX queue is drained at least half way */
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if (sc->ether.tx_full &&
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(sc->ether.tx_free_cnt >= (SBE_2T3E3_TX_DESC_RING_SIZE / 2))) {
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sc->ether.tx_full = 0;
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netif_wake_queue(sc->dev);
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}
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spin_unlock(&sc->ether.tx_lock);
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}
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void dc_intr_tx_underflow(struct channel *sc)
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{
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u32 val;
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dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
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val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE);
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dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS);
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switch (val & SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS) {
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case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1:
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
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SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2);
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break;
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case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_2:
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dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
|
|
SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3);
|
|
break;
|
|
case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_3:
|
|
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
|
|
SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4);
|
|
break;
|
|
case SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_4:
|
|
default:
|
|
dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
|
|
SBE_2T3E3_21143_VAL_STORE_AND_FORWARD);
|
|
break;
|
|
}
|
|
|
|
dc_transmitter_onoff(sc, SBE_2T3E3_ON);
|
|
}
|
|
|
|
|
|
|
|
|
|
void exar7250_intr(struct channel *sc)
|
|
{
|
|
u32 status, old_OOF;
|
|
|
|
#if 0
|
|
/* disable interrupts */
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE, 0);
|
|
#endif
|
|
|
|
old_OOF = sc->s.OOF;
|
|
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_STATUS);
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt! (REG[0x05] = %02X)\n", status);
|
|
|
|
switch (sc->p.frame_type) {
|
|
case SBE_2T3E3_FRAME_TYPE_E3_G751:
|
|
case SBE_2T3E3_FRAME_TYPE_E3_G832:
|
|
exar7250_E3_intr(sc, status);
|
|
break;
|
|
|
|
case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
|
|
case SBE_2T3E3_FRAME_TYPE_T3_M13:
|
|
exar7250_T3_intr(sc, status);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (sc->s.OOF != old_OOF) {
|
|
if (sc->s.OOF) {
|
|
if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE) {
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Disabling eth interrupts\n");
|
|
/* turn off ethernet interrupts */
|
|
dc_stop_intr(sc);
|
|
}
|
|
} else if (sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP) {
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Enabling eth interrupts\n");
|
|
/* start interrupts */
|
|
sc->s.OOF = 1;
|
|
dc_intr_rx(sc);
|
|
sc->s.OOF = 0;
|
|
if (sc->p.receiver_on) {
|
|
dc_receiver_onoff(sc, SBE_2T3E3_OFF);
|
|
dc_receiver_onoff(sc, SBE_2T3E3_ON);
|
|
}
|
|
dc_start_intr(sc);
|
|
}
|
|
}
|
|
#if 0
|
|
/* reenable interrupts */
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_BLOCK_INTERRUPT_ENABLE,
|
|
SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_ENABLE
|
|
);
|
|
#endif
|
|
}
|
|
|
|
|
|
void exar7250_T3_intr(struct channel *sc, u32 block_status)
|
|
{
|
|
u32 status, result;
|
|
|
|
if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_STATUS);
|
|
|
|
if (status) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt T3 RX (REG[0x13] = %02X)\n",
|
|
status);
|
|
|
|
result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
|
|
|
|
#if 0
|
|
if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_STATUS) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt T3: LOS\n");
|
|
sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_T3_RX_LOS ? 1 : 0;
|
|
|
|
}
|
|
#else
|
|
cpld_LOS_update(sc);
|
|
#endif
|
|
if (status & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_STATUS) {
|
|
sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt T3: OOF (%d)\n",
|
|
sc->s.OOF);
|
|
}
|
|
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_INTERRUPT_ENABLE,
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE);
|
|
#if 0
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_CP_BIT_ERROR_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_LOS_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_AIS_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_IDLE_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_FERF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_AIC_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_OOF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_P_BIT_INTERRUPT_ENABLE
|
|
#endif
|
|
}
|
|
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS);
|
|
if (status) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt T3 RX (REG[0x17] = %02X)\n",
|
|
status);
|
|
#if 0
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_T3_RX_FEAC_INTERRUPT_ENABLE_STATUS,
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_REMOVE_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_T3_RX_FEAC_VALID_INTERRUPT_ENABLE
|
|
);
|
|
#endif
|
|
}
|
|
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_LAPD_CONTROL);
|
|
if (status)
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt T3 RX (REG[0x18] = %02X)\n",
|
|
status);
|
|
}
|
|
|
|
|
|
if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_FEAC_CONFIGURATION_STATUS);
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x31] = %02X)\n",
|
|
status);
|
|
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_TX_LAPD_STATUS);
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt T3 TX (REG[0x34] = %02X)\n",
|
|
status);
|
|
}
|
|
}
|
|
|
|
|
|
void exar7250_E3_intr(struct channel *sc, u32 block_status)
|
|
{
|
|
u32 status, result;
|
|
|
|
if (block_status & SBE_2T3E3_FRAMER_VAL_RX_INTERRUPT_STATUS) {
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_1);
|
|
|
|
if (status) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt E3 RX (REG[0x14] = %02X)\n",
|
|
status);
|
|
|
|
result = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
|
|
|
|
#if 0
|
|
if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_STATUS) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt E3: LOS\n");
|
|
sc->s.LOS = result & SBE_2T3E3_FRAMER_VAL_E3_RX_LOS ? 1 : 0;
|
|
}
|
|
#else
|
|
cpld_LOS_update(sc);
|
|
#endif
|
|
if (status & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_STATUS) {
|
|
sc->s.OOF = result & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt E3: OOF (%d)\n",
|
|
sc->s.OOF);
|
|
}
|
|
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_1,
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE
|
|
);
|
|
#if 0
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_COFA_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_OOF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_LOF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_LOS_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_AIS_INTERRUPT_ENABLE
|
|
#endif
|
|
}
|
|
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_STATUS_2);
|
|
if (status) {
|
|
dev_dbg(&sc->pdev->dev,
|
|
"Framer interrupt E3 RX (REG[0x15] = %02X)\n",
|
|
status);
|
|
|
|
#if 0
|
|
exar7250_write(sc, SBE_2T3E3_FRAMER_REG_E3_RX_INTERRUPT_ENABLE_2,
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_FEBE_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_FERF_INTERRUPT_ENABLE |
|
|
SBE_2T3E3_FRAMER_VAL_E3_RX_FRAMING_BYTE_ERROR_INTERRUPT_ENABLE);
|
|
#endif
|
|
}
|
|
|
|
}
|
|
|
|
if (block_status & SBE_2T3E3_FRAMER_VAL_TX_INTERRUPT_STATUS) {
|
|
status = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_TX_LAPD_STATUS);
|
|
dev_dbg(&sc->pdev->dev, "SBE 2T3E3: Framer interrupt E3 TX (REG[0x34] = %02X)\n",
|
|
status);
|
|
}
|
|
}
|