ymohanma be4fc046be drm/i915: add VLV DSI PLL Calculations ... v2: - Grab dpio_lock mutex in vlv_enable_dsi_pll(). - Add and call vlv_disable_dsi_pll(). v3: Mostly based on Ville's review comments. - Only pipe A has DSI PLL lock bit. - Add more of CCK REG bit definitions for DSI PLL. - Make tables static. - Move clock gating out of the clock calculation functions. - DSI PLL LDO power gating. - Put alternative MNP from table calc behind #ifdef. v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville). Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-09-04 17:34:48 +02:00
..
drm	drm/i915: add VLV DSI PLL Calculations	2013-09-04 17:34:48 +02:00
host1x	drm/tegra: fix up page flip flags.	2013-09-02 09:47:56 +10:00
vga	vgaarb: Fix VGA decodes changes	2013-09-03 19:17:59 +02:00
Makefile